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TIDA-010242: MIL-STD-1275E Surge Protection Reference Design

Eli Hait54
Prodigy 220 points
Part Number: TIDA-010242
Other Parts Discussed in Thread: LM5069, LM7480

Hi,

My question relates MIL-STD-1275E Surge Protection Reference Design which using LM74800DRRRQ1 and LM5069MM-2 devices:

In the Design Guide TIDA-010242 is written "the output of the protection circuit should be nominal
28 V and maximum at 34 V" but nothing about the lowest VIN to operate properly.

In my application the used 24VDC input which may go down to 9V

Would this application schematic work properly when the input down to 9V?

  • 0
    TI__Intellectual 2790 points

    Eli,

    The design as is will not support down to 9V input. This is due to how the UVLO is configured on the LM5069. There are a few methods you can use to alter the design to support a lower input voltage however.

    1. Since 9V is the limit for the device, you can just tie the UVLO pin of the LM5069 to Vin of the device to set it to the minimum. This function is described in section 8.3.4 of the datasheet.

    2. A more through approach would be to design the UVLO and OVLO to meet your specific application needs (OVLO is disabled in the original design). The simplest way is to use the design calculator we have here: www.ti.com/.../LM5069QUICK-CALC

  • 0 in reply to Bart Basile
    Prodigy 220 points

    Hi, thanx for your fast response.

     So just by changing the UVLO and ULVO pins connection this design will operate downto 9V?

     Thanx,

    Eli.

  • 0 in reply to Bart Basile
    Prodigy 220 points

    According the OVLO input in LM5069: In the data sheet is written that "Overvoltage lockout: An external resistor divider from the system input voltage sets the overvoltage turnoff threshold. An internal 21-µA current source provides hysteresis. The disable threshold at the pin is 2.5 V." 

    I understand that this pin should be connected to the input via resistors divider resulting with 2.5V when input at 50V... But in the schematic it connected to GND, so it will always be in the overvoltage lockout state because the input is much below the threshold?

  • 0 in reply to Eli Hait54
    TI__Intellectual 2790 points

    Eli,

    That is correct. Stage one will pass the 9V though to stage two, which can be configured to also operate at your required pass voltage.

    The implementation in the design is actually following option D described in section 9.2.1.2.6.4 of the LM5069 dataset. By grounding the OVLO pin, it is disabled. Since the first stage output is limited by the LM7480, we don't need the OVLO function here, and are mainly interested in only UVLO and the clamping functionality. Keep in mind that the clamp voltage is set by D4.