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Tool/software: WEBENCH® Design Tools
Dear Sirs
Use LM5175 in the following project:
I enclose schematic and pcb in pdf format
VIN range 12-30V Vout 28V 15A 100Khz with a parallel of two inductor wurth 7443641000 10uH 37A 2.4 mOhm equivalent inductor 5uH 74A 1.2 mOhm.
With 13.5 V in input and 28 V in output the card works in buck-boost instead of working only in boost mode.
I think the main problem is that we developed it on 4-layer FR4, therefore the mosfet dissipation area does not allow to have short gate tracks.
One thing I checked between redoing the same project with the "LM5175 Buck-Boost Quickstart Tool - r9.xlsm" and with the "WBdesign" I get different results.
For example the compensation components (COMP pin) with the "WBdesign" I get 10Kohm + 15nF // 330pF with the "Buck-Boost Quickstart Tool - r9.xlsm"
I get 3K16 Kohm + 12nF // 39pF (NB by entering data of the inductance 5uH 1,2mOhm).
Another mistake we made is that of not having drawn tracks SW1 // HDRV1 and SW2 // HDRV2 side by side.
I would appreciate you to report any corrections before producing the next sample.
Best Regards
Orfeo MilaniSchematic Power.pdfPCB layout.pdf
Hi Youhao Xi
I modified the circuit like the new diagram attached because with the oscilloscope I detected a cross-conducting problem between Q32 // Q33 and Q35 // Q36 that damaged the LM5175 chip.
I replaced the LM5157 chip and I inserted R = 10 Ohm and a schottky diode to increase the dead times.
I'm testing the Boost CCM mode circuit so I disabled Q30, Q31, Q34.
The circuit is working with Vin = 13.5 V and Vout = 29V @ 15A.
Are the changes I have made possible or can they cause problems?
Is there any better solution?
Thanks,
Orfeo MilaniSchematic Power revB.pdf
Hi Orfeo,
Thank you for the updating. What you did is the right way to create a dead time: slowing down the turn-on by the resistor, and speeding up the turn off throuth the diode.
To make sure no more shoot-through would occur again, please monitor the high side and low side FET's Vgs and see there at least 20ns~30ns dead time between the two FET, measured at the FET's Vth level. Please avoid excessive dead time.
We do recommend to add 1 Ohm or so gate resistor before the FET is paralleled. So in this case, you should have the following configuration:
1 Ohm --> Gate1
DRV --> (D//R) --> <
1 Ohm --> Gate2
The "<" sign above means split into two lines, one to each 1Ohm to gate; "-->" is the signal flow direction. (Sorry the Webench does not allow me to draw in the window).
Thanks,
Youhao