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PMP6812: VC, Feedback Voltage, OR-ing,

HEESOO AHN
Prodigy 40 points
Part Number: PMP6812
Other Parts Discussed in Thread: TPS23754, , TPS23753A, TL431

To whom may it concern.

Hi, I'm HS. 

I've designed the PoE PD circuit which is using TPS23754 and referenced PMP6812. 

I've got some questions about PMP6812.

Since I'm new to this PoE design, Please bear with me and explain and spare you knowledge with me as detailed as possible.

Thank you for your hard work in advance.

1. VC

I've read VC is the bias voltage for DCDC Controller in the chip, TPS23754. But it's from the Tertiary winding.

1-1. I wonder why VC is derived from Tertiary winding?

1-2 What's the purpose of D13, R7 and? C22

I asssume R7 and C22 make LPF for suppressing the voltage spike when the signal in TRANSFORMER which has tertiary winding. Am i correct?

How do you calculate the value of these RCs?

1-3. What's the purpose of R8, R9, R10?

Especially, I'm confused with R9 and R10 because i can't tell which one is for current sensing, I assume R10 is the current sensing resistor tho..

2. Feedback

2-1 I wanna know the role of C24, R16, R12. How do you calculate their proper value??

2-2. I've read VB is 5.1V. Would it be ok if I connect a LED to VB for 'Power On' LED? Or should I connect LED to V_OUT(=12V)?? Which one would be better?

2-3. Basically, I just don't understand how U3 works. This forum and datasheet said it's feedback circuit tho Would you break it down little bit more?

2-4. Does opto-coupler(U2) play a key role in efficiency? I mean, can we maximize the efficiency if we use kinda better opto-coupler than TCMT1107?

Also, Please let me know how you set the RCs for U2

2-5. I read datasheet about BLNK, so called blanking but It was a 'Hm...' You may think I don't know how the game goes and you're dang right lol But yeah here we are, 

Would you explain what blanking is and why it is important and how it works??

3.OR-ing

I tried to find information about this DC JACK circuit.

I read some application reports and datasheets including SLVA306A but none of them are same as this design.

Would you enlighten me?? What's going on here?

  • 0
    TI__Intellectual 2350 points

    HS,

    A good place to start is with SLVA305C.  It goes through the complete design process for a diode rectified flyback converter operating from a PoE input.  The TPS23753A used in SLVA305C is very similar to the TPS23754.  The main difference is the TPS23754 can process higher power.  The basic design process and equations will be the same.

    VC:  The TPS23753A/54 have an internal start-up current source that supplies a few milliamps of current to charge C22 up to the UVLO level, which then turns on the PWM portion of the IC.  The IC power and gate drive current is supplied by C22 until the tertiary winding  ramps up to its regulation value.  Supplying all of the power to run the IC, gate drive, and VREF would dissipate too much power in the IC.  The tertiary winding is more efficient.  D13/C22 is the rectifier/filter for this output and is calculated just like the main output winding.  R7 absorbs some of the leakage inductance energy so the VC voltage doesn't increase when the main output is lightly loaded.  It's value is usually determined during testing.  It's value is usually less than 50 ohms, otherwise there will be too much voltage drop across it and it will dissipate too much power.

    R8 limits the gate current to slow down the switching of Q1.  This is mainly to reduce EMI.  Sometimes there will be an anti-parallel diode to provide a slow turn-on through R8 and fast turn-off through the diode.

    R10 is the current sense resistor used to generate the CS signal for peak current mode control.  R9 has a number of functions.  If there are negative voltage spikes on the CS signal it limits the reverse current going into the CS pin.  Also, there is a ramp current sourced from the CS pin that flows through R9 generating a slope compensation voltage ramp that is added to the CS signal.  This isn't required for duty cycles less than 50%, but still helps provide a larger CS signal to avoid noise issues at light loading.

    Sometimes there will be a small capacitor from CS to ground, forming a R/C filter with R9.  It wasn't needed here because the TPS23754 has leading edge blanking.  There is a voltage spike across R10 at turn-on due to gate drive current and initial Q1 drain current.  If this voltage spike is too large it may indicate a false overcurrent.  Leading edge blanking holds the CS pin low for the blanking period so that the control circuit does not see this leading edge voltage spike on CS.

    VB:  The current that VB can supply is limited to 5mA max.  Since it is already used to power the opto bias, it is best not to power anything else from VB.  It would be best to power the LED from V_OUT.

    Feedback:  R12 is the pull-up for the optocoupler bias.  When CTL is high (VB=5V) the PWM is at max duty cycle.  When CTL is low (1.5Vtyp on TPS23754) the PWM is at 0% duty cycle.  R12 in conjunction with R16 and C24 are also used in the control loop compensation.  The biasing of U2 (calculating the values of R12 and R17) and the loop compensation is covered in SLVA305C.  U3 is the error amplifier.  It contains a 2.495V reference and a shunt voltage regulator.  The converter output voltage is sampled using R18/R24 and input to the negative input of the internal opamp of the TL431.  When the output is too high, the voltage on the cathode of the TL431 moves lower, increasing the current through the opto diode.  This results in an increase in the transistor current of the opto.  The voltage drop across R12 is then larger, resulting in a lower CTL voltage.  This reduces the duty cycle which then lowers the output voltage back to the regulated value.

    The selection of U2 will have little to no effect on efficiency.  It is best to use an opto with a limited range of gain, such as 80-160 or 100-200.  If an opto with a large gain/gain range is used, such as 50-500, the loop gain can also change by this amount and make stabilizing the loop difficult.

    The DC jack input is the same as Option 2 in SLVA306A.  When the voltage on APD is higher than 1.5V, the hot swap FET inside the TPS23754 turns off.  The converter power is then supplied from the DC jack voltage.  D9 blocks current flowing from the PoE input into the DC jack input when the DC jack voltage is lower.

    I hope this helps you understand the TPS23754 operation, design and design process better.

    Thanks,

    David

  • 0 in reply to David Strasser
    Prodigy 40 points

    Hi David.

    Thank you for your proficient knowledge and it helped me a lot tho I've got some more questions.

    VC:  The TPS23753A/54 have an internal start-up current source that supplies a few milliamps of current to charge C22 up to the UVLO level, which then turns on the PWM portion of the IC.  The IC power and gate drive current is supplied by C22 until the tertiary winding  ramps up to its regulation value.  Supplying all of the power to run the IC, gate drive, and VREF would dissipate too much power in the IC.  The tertiary winding is more efficient.  D13/C22 is the rectifier/filter for this output and is calculated just like the main output winding.  R7 absorbs some of the leakage inductance energy so the VC voltage doesn't increase when the main output is lightly loaded.  It's value is usually determined during testing.  It's value is usually less than 50 ohms, otherwise there will be too much voltage drop across it and it will dissipate too much power.

    --> 1. What is VREF in this context?

    R9 has a number of functions.  If there are negative voltage spikes on the CS signal it limits the reverse current going into the CS pin.  Also, there is a ramp current sourced from the CS pin that flows through R9 generating a slope compensation voltage ramp that is added to the CS signal.  This isn't required for duty cycles less than 50%, but still helps provide a larger CS signal to avoid noise issues at light loading.

    --> 2-1. I don't understand how R9 can protect the negative voltage spike. Would you break it down little bit more for me?

    As far as I know, Usually didoes protect the negative spikes, don't they?

    2-2. This is the screenshot of TPS23754 block diagram. You mentioned CS can source the current to Gate of Q1 throught R9 but i can't see how it works. Would you explain how CS can be a output pin where it can source the current?

    Sometimes there will be a small capacitor from CS to ground, forming a R/C filter with R9.  It wasn't needed here because the TPS23754 has leading edge blanking.  There is a voltage spike across R10 at turn-on due to gate drive current and initial Q1 drain current.  If this voltage spike is too large it may indicate a false overcurrent.  Leading edge blanking holds the CS pin low for the blanking period so that the control circuit does not see this leading edge voltage spike on CS.

    3-1 Could you possibly explain what the leading edge blanking is and how it works? 

    3-2 Why does the voltage spike across R10 occur? I don't understand the second line clearly.

    4. Feedback

    4. Would you explain the purpose of D14 and R13?

    I assume R13(0 ohm) is for debugging but would you tell me what the purpose is?

    The DC jack input is the same as Option 2 in SLVA306A.  When the voltage on APD is higher than 1.5V, the hot swap FET inside the TPS23754 turns off.  The converter power is then supplied from the DC jack voltage.  D9 blocks current flowing from the PoE input into the DC jack input when the DC jack voltage is lower.

    --> So we need the voltage higher than 1.5V to use the DC JACK(Adapter). My question is...then why do we need 5.1V zener diode here? 

    Is there any reason for using 5.1V rather than around 1.5V or slight higher than 1.5V?

    Thank you for your hard work and I really appreciate it!

    All the best

  • 0 in reply to HEESOO AHN
    TI__Intellectual 2350 points

    1.  VREF is the reference voltage, labeled VB on the TPS23754.

    2-1.  R9 doesn't limit the negative voltage spike, it just limits the amount of current that can flow into the IC if there is a negative spike.  Yes, there are internal protection diodes.

    2-2.  There is the 40uApk current source that flows through the internal 3.75k resistor, then through the external resistor R9, then through the sense resistor R10 to RTN.

    3-1, 3-2.  When the primary FET turns on, there are many parasitic capacitances that discharge through the FET and current sense resistor.  The diode in the RCD clamp on the primary and the secondary rectifier also have reverse recovery time during which current is flowing through the FET/sense resistor.  The gate current used to charge the FET gate capacitance also flows through the current sense resistor.  The sense resistor will have parasitic inductance in addition to resistance.  All of these currents create a leading edge voltage spike across the current sense resistor.  Leading edge blanking holds the CS pin low for the programmed period of time so that the control circuit does not see this leading edge spike and register a false overcurrent.

    4. R13 is used to inject a test signal for control loop measurement.  Its value varies with the test equipment being used, but is usually in the 10-50 ohm range.  R14/C28/D14 is secondary soft-start.  It slowly ramps up the feedback signal to prevent overshoot of the output voltage at turn-on.  The top half of D14 discharges C28 at turn-off.  For the PMP6812 design the 5.1V Zener diode on APD is not required.  The voltage on the APD pin is limited to 6.5Vmax.  If the DC jack input were a wide range, say 10.8-57Vdc, the resistor divider would need to be set to provide 1.5V at APD for 10.8V input.  At 57V input the APD voltage would then be higher than the 6.5Vmax rating and the 5.1V Zener diode would be required.

    Thanks,

    David

  • 0 in reply to David Strasser
    Prodigy 40 points

    2-1.  R9 doesn't limit the negative voltage spike, it just limits the amount of current that can flow into the IC if there is a negative spike.  Yes, there are internal protection diodes.

    --> What would be the main cause of negative voltage spike in PoE system??

    2-2.  There is the 40uApk current source that flows through the internal 3.75k resistor, then through the external resistor R9, then through the sense resistor R10 to RTN.

    --> I still don't understand the purpose of the current source. Would you enlighten me about the current source and CS procedure?

    4. R13 is used to inject a test signal for control loop measurement.  Its value varies with the test equipment being used, but is usually in the 10-50 ohm range.  R14/C28/D14 is secondary soft-start.  It slowly ramps up the feedback signal to prevent overshoot of the output voltage at turn-on.  The top half of D14 discharges C28 at turn-off. 

    --> Would it be ok if I leave out R13?

    --> Let's say Pin 4 of U3 as V_REF, Pin 3 of U3 as Vx(Voltage of Cathode). 

    I assume Vx is set as (1+R18/R24)*V_REF which is 12V as same as V_OUT.

    The voltage of C28 would be 0 at the very first time and it would be charged "Softly" by V_OUT(12V) through R14 

    Meanwhile, the top half of D14 would be reverse biased and the bottom one would be biased and Vx will follow the voltage of C28. 

    This is the flow i understand so far. But i can't think of it further since i can't tell when the bottom one will be reverse biased..

    I'm not even sure the flow above is correct or not.

    Basically, which one would be higher, The voltage of C28 or Vx?

    Would you explain the procedure of soft-start as detailed as possible for me?

    Lastly, so as far as i understand, 'Leading edge blanking' is the technique that you neglect the voltage spike when signal switches for good amount of time. Would you confirm that it's correct?

    I appreciate your help. Thank you in advance!

  • 0 in reply to HEESOO AHN
    TI__Expert 5435 points

    Hi Heesoo,

    Thanks for your questions and interest in our designs. We are trying our best to answer all of the questions, but the best option is to spend some time reading the datasheet and some power electronics background material.

    If you have a specific question about PMP6812 we can help to answer that. However for general knowledge please post another question tied to the product (TPS23754) so that we can get it to the right team to answer.

    Thank you.

    Robert