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Tool/software: WEBENCH® Design Tools
Hi Team,
I simulated two condition of TPS43060. I attached two file. I modified the compensation and filter parameters. But when I did the load transient simulation, I find that large Phase Margin will have the large pk to pk voltage. I think it's not make sense to me. Could you let me know why larger PM but cause larger pk-pk transient value.
Regards,
Roy
HI Roy,
Please note that in your modifications the steady state Vout is no longer at 21V. Hence it is little difficult to compare these designs. In case you want to proceed with the modified design, please readjust your BOM to get 21V.
while trying to improve phase margin you have significantly reduced the output capacitor as well as the bandwidth (cross over frequency). The new Cout is less than half of original value. even though phase margin is improved, load transient is a strong function of output capacitor. Hence reducing Cout has slightly increased the overshoot and undershoot.
Regards,
Vishwanath
Hi Vishwanath,
Thank you for your information. So in these two design, Cout will judge the load transient response, is it right?
I considered the load transient is related to PM and BW originally. So Cout will have impact in load transient, do you have application note to show the impact? So below image is created by same output filter, is it right?
Regards,
Roy
Hi Roy,
Since this is a public forum, I've shared equations governing relation between overshoot and Cout over Email. I'll be closing this thread. please respond to the email if you have further queries.
Regards,
Vishwanath