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TIDA-00901: A better connection for de-coupling capacitors

Part Number: TIDA-00901

Hello,

May I ask your advice on the connection for decoupling capacitors in TIDA-00901. In this design reference, three de-coupling capacitors C1, C2, and C3 are connected from PVDD to ground. I am wondering whether it would be better to connect these three capacitors from PVDD to SL_A/SL_B/SL_C. Since the purpose of these de-coupling capacitors is to attenuate high frequency currents caused by switching from the MOSFETs and other parasitic capacitances, it would be better to de-coupling the inductance from the connection traces 1) to drain pin of the high-side MOSFET, 2) between the source pin of the high-side MOSFET and drain pin of the low-side MOSFET, and 3) between course pin of the low-side MOSFET and SL_A/SL_B/SL_C. Connecting CA/C2/C3 to SL_A/SL_B/SL_C makes the de-coupling loop shorter, which is ideal. Current connection from PVDD to ground has much longer loop due to the low-side shunt. I am wondering whether there is any simulations being done in comparing these two connections.

Thanks and I look forward to hearing from you,

John

  • John,

    The board GND plane is well defined and is very close to the SL_x nodes. Sense resistors are low inductance and the routing between sense resistors and GND is also low impedance. We route the bulk capacitors to GND since we do not want them to have to ride on the voltage that the sense resistors see on their non-GND side.

    Regards,

    -Adam