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CC2650MODA: TI-provided BLE Stack does not meet NPI communication specifications

Part Number: CC2650MODA
Other Parts Discussed in Thread: BLE-STACK, AM3352

Hi Expert,

I am communicating with the CPU and BLE Module, but I have confirmed that the SRDY signal during continuous communication from BLE does not meet the timing requirements for continuous communication from the slave described in the NPI User Guide. The details are as follows.

<Communication conditions>
 -Method: Network Processor Interface

 -Master: CPU (AM3352bzcz)

 -Slave: BLE module (CC2650MODA)

<High time of SRDY signal>
 -NPI User Guide Requirement: 270usmin

 -Measured value: about 66us to 90us

The software for the BLE module uses the following provided by TI.

SDK version: BLE-Stack 2.2.7 (folder name: ble_sdk_2_02_07_06)

Project: \ble_sdk_2_02_07_06\examples\cc2650bp\simple_np

Where should I modify the TI supplied software to meet the timing requirements?

Thanks

Sakai

  • Hi Sakai,

    Thank you for reaching out.

    <High time of SRDY signal>
     -NPI User Guide Requirement: 270usmin

    In order to be sure I fully understand your request, may I kindly ask you to specify which device sets this requirement? It would be really helpful if you could share links and references toward this requirement.

    In the NPI software, the UART operations are handled by the file npi_tl_uart.c

    Best regards,

  • Hi Clément,

    Thank you for your responce.

    We believe that we need to meet the timing requirements listed in the BLE Stack User guide for CC2650MODA.
    Below are the NPI requirements described in the BLE Stack User guide for CC2650MODA and the link to the NPI User Guide.

    NPI(UNPI) Handshake : Network Processor Interface (NPI) — SimpleLinkTm CC13x2 / CC26x2 SDK BLE5-Stack User's Guide 2.01.02.00 documentation

    NPI User Guide : NPI User Guide.pdf (ti.com)

    If you have any other questions, please contact us.

    Thanks,

    Sakai

  • Hi Sakai,

    Thank you for the details provided. Please note the timings provided in the referenced document are based on testing. These do not represent absolute values but instead are values that were tested and shown to be functional.

    The SRDY signal is actually handled by the file npi_tl.c.
    In order to move further, I would recommend to identify the line of code responsible to set and then reset the SRDY signal when you encounter the behavior reported.
    => Looking at the code, I assume line "SRDY_ENABLE();" in NPITL_handleMrdyEvent is responsible to set SRDY when "(npiTxActive && mrdyPktStamp == txPktCount )" is true.

    void NPITL_handleMrdyEvent(void)
    {
        ICall_CSState key;
        key = ICall_enterCriticalSection();
    
        // Check to make sure this event is not occurring during the next packet
        // transmission
        if ( PIN_getInputValue(MRDY_PIN) == 0 ||
            (npiTxActive && mrdyPktStamp == txPktCount ) )
        {
            transportMrdyEvent();
            SRDY_ENABLE();
        }
    
        ICall_leaveCriticalSection(key);
    }

    After this, SRDY is reset within NPITL_transmissionCallBack (using the line "SRDY_DISABLE();").

    Please double check when executing the code on your device.

    Assuming you can confirm my assumption, you can slightly modify the code in order to set a flag when setting the SRDY signal under the conditions identified. Then, when the mentioned flag is set, instead of resetting the SRDY signal in NPITL_transmissionCallBack, you start a timer and reset it after its expiration.

    I hope this will help,

    Best regards,

  • Hi Clément,

    Thank you for your responce.

    It took some time for internal consideration.

    It was pointed out that the reference document does not list absolute values, so I would like to check whether the signal can be captured without any problems according to the specifications of AM3352. I found a description from the AM3352 manual that it takes 2 clocks if the interrupt is set at the edge. I think the above clock is the AM3352's internal clock for GPIO, but is this clock the same as the clock input from OSC0_IN? Could you tell me if there is a register that can change the setting of the internal clock?

    Thanks,
    Sakai

  • Hi Sakai,

    May I kindly ask you to open a new thread to discuss the advanced configuration of the AM3352? This way experts of this device will provide assistance.

    Thank you for your comprehension.

    Best regards,

  • Hi Clément,

    Thank you for your response.
    I will start a new thread related to AM3352.

    Thanks,
    Sakai