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TRF7960: Issue with the value of SYS_CLK generated from TRF7960

Y M
Prodigy 20 points
Part Number: TRF7960
Other Parts Discussed in Thread: MSP430F2370,

Hi all,

The hardware schematic we are using is TRF7960 feeding the clock for MSP430F2370 (cf ti document slou 186g).

The issue is located in the value of SYS_CLK from TRF7960 which is always 3.39 MHz, even when the component is configured to provide 6.78 MHz or 13.56 MHz, when the JTAG is NOT connected.

However when the JTAG is connected, the value of SYS_CLK from TRF7960 is the one configured by the sw (3.39, or 6.68 or 13.56).

I guess it might an issue in delay of configuration of the TRF7960 by MSP430F2370, but I can not figure out at which step.

Do you have any advices to understand and solve this issue ?

  • 0
    TI__Genius 13055 points

    Hello Customer, thank you for your question and interest in our products.

    The forum support of this product has been reduced to first reference our existing documentation and collateral. For support, please take a look to the “Similar Topics” section at the lower right of the thread page. In addition, please consult the existing collateral in the “Technical Documentation” section of the TRF7960 product web page. Alternatively, you can use the search engine of your choice to look for related E2E threads. With each of these resources we believe it will help with your question. Please also be aware that TI recommends to use the TRF7970A or TRF7964A for new designs.

  • 0 in reply to Andreas Mueller
    Prodigy 20 points

    Thanks for the reply.
    Unfortunately I am actually updating a old hw design and does not have the chance to update the TRF7960.

    I checked "similar topics" but I did not find anything related to an issue with SYS_CLK.