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CC2340R5: Compatility with the CC2500 and support of 2-FSK and GFSK with low data rates

Odhran Cummings
Prodigy 10 points
Part Number: CC2340R5
Other Parts Discussed in Thread: CC2500

Tool/software:

Hi,

I am looking to use the CC2340R5 in a project that will support BLE communications, as well as support proprietary communications with an old receiving device that uses the CC2500. Looking at other questions on the forum regarding the CC2500 and CC2340, they seem to be somewhat compatible, but not entirely. 

Using smartRF studio 8, it seems that the CC2340 is only capable of GFSK and MSK modulation. Is 2-FSK, as used in the CC2500 not supported? If not, why not? Since it is similar to GFSK I assumed it would be possible.

Also, as said, GFSK is supported, but in smartRF studio I am unable to adjust the symbol rate. I would like to use a lower symbol rate, something like 2.4kbps. Is this possible? If not, I'm just curious why.

Lastly, is the FEC implemented on the CC2500 implementable on the CC2340?

Thank you in advance.

  • 0
    TI__Guru**** 208457 points

    Hi Odhran,

    Here are two relevant E2E threads you've likely already reviewed:

    https://e2e.ti.com/f/1/t/1336461 
    https://e2e.ti.com/f/1/t/1280899 

    The PHY that you are asking for is not currently validated by TI and thus not provided in the SmartRF Studio 8 software.  This will update as validated PHYs are added to the CC2340RX device family.  I am asking internally whether there are any additional RF PHYs being planned but I am not confident that your requirements will be included.

    Regards,
    Ryan

  • 0 in reply to Ryan Brown1
    TI__Expert 8521 points

    Hello,

    The closest PHY we offer on the CC2340R5 is the 20 kbps FSK PHY, attached is the rfconfig export with CC2500 whitening and FEC enabled. Please let me know if this works for you.

    Please keep in mind that the 20 kbps PHY on the CC2340R5 does not have any RX capability, meaning you can only use it for TX on the CC2340R5. 

    rcl_settings_fsk_20_kbps_fec.h

    rcl_settings_fsk_20_kbps_fec.c 
    // SETTINGS FOR PHY BASED ON RADIO CONTROL LAYER (SOURCE FILE)
//
//
// CODE EXPORT INFORMATION
// This file is generated
//
// Tool name                   SmartRF Studio 8
// Tool version                1.0.2.39
// Created                     2024-08-28 11:39:09.796
// Computer                    LT5CG2132LP5
// User                        
//
//
// WORKSPACE INFORMATION
//
// Workspace file              -
// Device                      CC2340R5
//     Package                 QFN40 5x5 RKP
//     Revision(s)             B (2.0)
// SDK                         SimpleLink LPF3 SDK 8.20.00
// Board                       LP-EM-CC2340R5
// PHY                         Custom FSK 20 kbps, TX
// PHY abbreviation            fsk_20_kbps
//
//
// PHY PROPERTIES
//
// Run-time properties:
//     Frequency               2440.00000 MHz
//     TX output power         5.0 dBm 
// Start of packet:
//     Synchronization word    0xD391D391 
// Packet data:
//     Whitening               CC2500 compatible 
//     Payload length          Variable, 8-bit length field 
//
//
// VALIDATION WARNINGS
//
// No warnings

#include "rcl_settings_fsk_20_kbps.h"
#include DeviceFamily_constructPath(rf_patches/lrf_pbe_binary_generic.h)
#include DeviceFamily_constructPath(rf_patches/lrf_mce_binary_genfsk.h)
#include DeviceFamily_constructPath(rf_patches/lrf_rfe_binary_genfsk.h)


// Command: Packet TX - CMD_GENERIC_TX - Generic transmit command
RCL_CmdGenericTx rclPacketTxCmdGenericTxFsk20Kbps =
{
    .common.cmdId                         = RCL_CMDID_GENERIC_TX,                
    .common.phyFeatures                   = 0x0000,                              
    .common.scheduling                    = RCL_Schedule_Now,                    
    .common.status                        = RCL_CommandStatus_Idle,              
    .common.conflictPolicy                = RCL_ConflictPolicy_AlwaysInterrupt,  
    .common.allowDelay                    = 0x00,                                
    .common.runtime.handler               = RCL_Handler_Generic_Tx,              
    .common.runtime.client                = (RCL_Client*) 0,                     
    .common.runtime.lrfCallbackMask.value = 0x00000000,                          
    .common.runtime.rclCallbackMask.value = 0x00000000,                          
    .common.runtime.callback              = (RCL_Callback) 0,                    
    .common.timing.absStartTime           = 0x00000000,                          
    .common.timing.relMinTime             = 0x00000000,                          
    .common.timing.relGracefulStopTime    = 0,                                   
    .common.timing.relHardStopTime        = 0x00000000,                          
    .rfFrequency                          = 0x916F7200,                          
    .txBuffers.head                       = (List_Elem*) 0,                      
    .txBuffers.tail                       = (List_Elem*) 0,                      
    .syncWord                             = 0xD391D391,                          
    .txPower.fraction                     = 0x0,                                 
    .txPower.dBm                          = 5,                                   
    .config.fsOff                         = 0x1                                  
};

// Command: Packet TX - CMD_GENERIC_TX_REPEAT - Generic repeated packet transmit command
RCL_CmdGenericTxRepeat rclPacketTxCmdGenericTxRepeatFsk20Kbps =
{
    .common.cmdId                         = RCL_CMDID_GENERIC_TX_REPEAT,         
    .common.phyFeatures                   = 0x0000,                              
    .common.scheduling                    = RCL_Schedule_Now,                    
    .common.status                        = RCL_CommandStatus_Idle,              
    .common.conflictPolicy                = RCL_ConflictPolicy_AlwaysInterrupt,  
    .common.allowDelay                    = 0x00,                                
    .common.runtime.handler               = RCL_Handler_Generic_TxRepeat,        
    .common.runtime.client                = (RCL_Client*) 0,                     
    .common.runtime.lrfCallbackMask.value = 0x00000000,                          
    .common.runtime.rclCallbackMask.value = 0x00000000,                          
    .common.runtime.callback              = (RCL_Callback) 0,                    
    .common.timing.absStartTime           = 0x00000000,                          
    .common.timing.relMinTime             = 0x00000000,                          
    .common.timing.relGracefulStopTime    = 0,                                   
    .common.timing.relHardStopTime        = 0x00000000,                          
    .rfFrequency                          = 0x916F7200,                          
    .txEntry                              = (RCL_Buffer_DataEntry*) 0,           
    .syncWord                             = 0xD391D391,                          
    .timePeriod                           = 0x00000000,                          
    .numPackets                           = 0x0064,                              
    .txPower.fraction                     = 0x0,                                 
    .txPower.dBm                          = 5,                                   
    .config.fsOff                         = 0x1,                                 
    .config.fsRecal                       = 0x1                                  
};


// Configuration: Common
static const uint32_t LRF_commonRegConfig[] =
{
    0x00000047,                               // Segment length = 71
    0x0000A002,                               //     Data structure 32-bit region (start byte position = 0, count = 3)
    (uint32_t) &LRF_swConfigFsk20Kbps,        //         LRF_swParam : swConfig
    (uint32_t) &LRF_txPowerTableFsk20Kbps,    //         LRF_swParam : txPowerTable
    (uint32_t) &(fcfg->appTrims),             //         LRF_swParam : trimDef
    0x14482006,                               //     HW 32-bit region (start address = 0x1448, count = 7)
    0x00000037,                               //         LRFDPBE.MDMCMDPAR1                  LRFDPBE.MDMCMDPAR0
    0x0000AAAA,                               //         < GAP >                             LRFDPBE.MDMCMDPAR2
    0x10800000,                               //         LRFDPBE.POLY0H                      LRFDPBE.POLY0L
    0x80050000,                               //         LRFDPBE.POLY1H                      LRFDPBE.POLY1L
    0x00210000,                               //         LRFDPBE.FCFG0                       LRFDPBE.PHACFG
    0x008600C4,                               //         LRFDPBE.FCFG2                       LRFDPBE.FCFG1
    0x00430080,                               //         LRFDPBE.FCFG4                       LRFDPBE.FCFG3
    0x14682000,                               //     HW 32-bit region (start address = 0x1468, count = 1)
    0x00020004,                               //         LRFDPBE.TXFWBTHRS                   LRFDPBE.RXFRBTHRS
    0x10DC1001,                               //     HW 16-bit region (start address = 0x10DC, count = 2)
    0x000B0002,                               //         LRFDPBE.TIMPRE                      LRFDPBE.TIMCTL
    0x00003005,                               //     HW sparse region (address/value pairs, count = 6)
    0x20C8001F,                               //         LRFDMDM.MODSYMMAP0
    0x21240A18,                               //         LRFDMDM.SPARE0
    0x212C0000,                               //         LRFDMDM.SPARE2
    0x30880000,                               //         LRFDRFE.RSSIOFFSET
    0x31201820,                               //         LRFDRFE.MISC0
    0x31300C07,                               //         LRFDRFE.PHEDISC
    0x20D41002,                               //     HW 16-bit region (start address = 0x20D4, count = 3)
    0x090F0199,                               //         LRFDMDM.BAUDPRE                     LRFDMDM.BAUD
    0x00000000,                               //         -                                   LRFDMDM.MODMAIN
    0x30941005,                               //     HW 16-bit region (start address = 0x3094, count = 6)
    0x34F21307,                               //         LRFDRFE.SPARE0                      LRFDRFE.MAGNCTL1
    0x3F13002E,                               //         LRFDRFE.SPARE2                      LRFDRFE.SPARE1
    0x00000AB0,                               //         LRFDRFE.SPARE4                      LRFDRFE.SPARE3
    0x30B01002,                               //     HW 16-bit region (start address = 0x30B0, count = 3)
    0x0006000A,                               //         LRFDRFE.IFAMPRFLDO                  LRFDRFE.LNA
    0x00000000,                               //         -                                   LRFDRFE.PA0
    0x30C40005,                               //     HW zero region (start address = 0x30C4, count = 6)
    0x30E4100C,                               //     HW 16-bit region (start address = 0x30E4, count = 13)
    0x00000200,                               //         LRFDRFE.DCO                         LRFDRFE.ATSTREFH
    0x00000008,                               //         LRFDRFE.DIVLDO                      LRFDRFE.DIV
    0x00000000,                               //         LRFDRFE.DCOLDO0                     LRFDRFE.TDCLDO
    0x07060000,                               //         LRFDRFE.PRE0                        LRFDRFE.DCOLDO1
    0x06050000,                               //         LRFDRFE.PRE2                        LRFDRFE.PRE1
    0x40080603,                               //         LRFDRFE.CAL0                        LRFDRFE.PRE3
    0x00007F00,                               //         -                                   LRFDRFE.CAL1
    0x31381002,                               //     HW 16-bit region (start address = 0x3138, count = 3)
    0x047FDF7F,                               //         LRFDRFE.PLLMON1                     LRFDRFE.PLLMON0
    0x00001804,                               //         -                                   LRFDRFE.MOD0
    0x31480005,                               //     HW zero region (start address = 0x3148, count = 6)
    0x34B02002,                               //     HW 32-bit region (start address = 0x34B0, count = 3)
    0x15050100,                               //         LRFDRFE.DTX7                        LRFDRFE.DTX6
    0x42413D2D,                               //         LRFDRFE.DTX9                        LRFDRFE.DTX8
    0x42424242,                               //         LRFDRFE.DTX11                       LRFDRFE.DTX10
    0x20206005,                               //     RAM 32-bit region (start address = 0x2020, count = 6)
    0x00B40001,                               //         PBE_GENERIC_RAM.SYNTHCALTIMEOUT     PBE_GENERIC_RAM.PHY
    0x00100F88,                               //         PBE_GENERIC_RAM.NUMCRCBITS          PBE_GENERIC_RAM.PKTCFG
    0x00024BB0,                               //         PBE_GENERIC_RAM.EXTRABYTES          PBE_GENERIC_RAM.FIFOCFG
    0x0000000F,                               //         < GAP >                             PBE_GENERIC_RAM.WHITEINIT
    0xFFFF0000,                               //         PBE_GENERIC_RAM.CRCINITH            PBE_GENERIC_RAM.CRCINITL
    0x00000100,                               //         PBE_GENERIC_RAM.LENOFFSET           PBE_GENERIC_RAM.LENCFG
    0x68046005,                               //     RAM 32-bit region (start address = 0x6804, count = 6)
    0x03000012,                               //         RFE_COMMON_RAM.TDCCAL0              RFE_COMMON_RAM.SYNTHCTL
    0x00100000,                               //         RFE_COMMON_RAM.TDCCAL2              RFE_COMMON_RAM.TDCCAL1
    0x569B0400,                               //         RFE_COMMON_RAM.K1LSB                RFE_COMMON_RAM.TDCPLL
    0x012D010A,                               //         RFE_COMMON_RAM.K2BL                 RFE_COMMON_RAM.K1MSB
    0x132C0034,                               //         RFE_COMMON_RAM.K3BL                 RFE_COMMON_RAM.K2AL
    0x916F07AB,                               //         RFE_COMMON_RAM.K5                   RFE_COMMON_RAM.K3AL
    0x68206005,                               //     RAM 32-bit region (start address = 0x6820, count = 6)
    0x00000000,                               //         RFE_COMMON_RAM.RTRIMMIN             RFE_COMMON_RAM.RTRIMOFF
    0x48080008,                               //         RFE_COMMON_RAM.DIVF                 RFE_COMMON_RAM.DIVI
    0x00000000,                               //         RFE_COMMON_RAM.DIVLDOF              RFE_COMMON_RAM.DIVLDOI
    0x00470014,                               //         RFE_COMMON_RAM.LDOSETTLE            RFE_COMMON_RAM.DIVLDOIOFF
    0x0005002E,                               //         RFE_COMMON_RAM.DCOSETTLE            RFE_COMMON_RAM.CHRGSETTLE
    0x0000FE00                                //         RFE_COMMON_RAM.IFAMPRFLDODEFAULT    RFE_COMMON_RAM.IFAMPRFLDOTX
};


// LRF register configuration list
static const LRF_RegConfigList LRF_regConfigList = {
    .numEntries = 1,
    .entries = {
        (LRF_ConfigWord*) LRF_commonRegConfig 
    }
};

// LRF_TxShape data structure
const LRF_TxShape LRF_shapeBaseGfsk20Fsk20Kbps = {
    .scale                 = 0x10101,
    .numCoeff              = 0x000B,
    .coeff                 = { 0x02, 0x12, 0x50, 0xAF, 0xED, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } 
};

// LRF_SwConfig data structure
const LRF_SwConfig LRF_swConfigFsk20Kbps = {
    .rxIntFrequency        = 500000,
    .rxFrequencyOffset     = 0,
    .txFrequencyOffset     = 500000,
    .modFrequencyDeviation = 0x00004A38,
    .txShape               = &LRF_shapeBaseGfsk20Fsk20Kbps,
    .bwIndex               = 0x00,
    .bwIndexDither         = 0x00 
};

// LRF_TxPowerTable data structure
const LRF_TxPowerTable LRF_txPowerTableFsk20Kbps = {
    .numEntries            = 0x0000000E,
    .powerTable            = {
        { .power = { .fraction = 0, .dBm = -20 }, .tempCoeff = 0, .value = { .reserved = 0, .ib = 18, .gain = 0, .mode = 0, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = -16 }, .tempCoeff = 0, .value = { .reserved = 0, .ib = 20, .gain = 1, .mode = 0, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = -12 }, .tempCoeff = 5, .value = { .reserved = 0, .ib = 17, .gain = 3, .mode = 0, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = -8 }, .tempCoeff = 12, .value = { .reserved = 0, .ib = 17, .gain = 4, .mode = 0, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = -4 }, .tempCoeff = 25, .value = { .reserved = 0, .ib = 17, .gain = 5, .mode = 0, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = 0 }, .tempCoeff = 40, .value = { .reserved = 0, .ib = 19, .gain = 6, .mode = 0, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = 1 }, .tempCoeff = 65, .value = { .reserved = 0, .ib = 30, .gain = 6, .mode = 0, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = 2 }, .tempCoeff = 41, .value = { .reserved = 0, .ib = 39, .gain = 4, .mode = 1, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = 3 }, .tempCoeff = 43, .value = { .reserved = 0, .ib = 31, .gain = 5, .mode = 1, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = 4 }, .tempCoeff = 50, .value = { .reserved = 0, .ib = 37, .gain = 5, .mode = 1, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = 5 }, .tempCoeff = 55, .value = { .reserved = 0, .ib = 27, .gain = 6, .mode = 1, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = 6 }, .tempCoeff = 75, .value = { .reserved = 0, .ib = 38, .gain = 6, .mode = 1, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = 7 }, .tempCoeff = 80, .value = { .reserved = 0, .ib = 25, .gain = 7, .mode = 1, .noIfampRfLdoBypass = 0 } },
        { .power = { .fraction = 0, .dBm = 8 }, .tempCoeff = 180, .value = { .reserved = 0, .ib = 63, .gain = 7, .mode = 1, .noIfampRfLdoBypass = 0 } } 
    }
};

// LRF_Config data structure
const LRF_Config LRF_configFsk20Kbps = {
    .pbeImage              = (const LRF_TOPsmImage*) LRF_PBE_binary_generic,
    .mceImage              = (const LRF_TOPsmImage*) LRF_MCE_binary_genfsk,
    .rfeImage              = (const LRF_TOPsmImage*) LRF_RFE_binary_genfsk,
    .regConfigList         = &LRF_regConfigList 
};

    Thanks,
    Alex F

  • 0 in reply to Alex Fager
    Prodigy 10 points

    Hello Ryan and Alex,

    Thank you very much for your responses. 

    The 20kbps FSK PHY with CC2500 compatible whitening and FEC mentioned by Alex is much more towards the proprietary PHY that I require for this design. However, as said, ideally it would be 2.4kbps rather than 20kbps. The reason for this is because the CC2500 has the lowest noise floor with 2.4kbps 2-FSK, and link budget and range is most critical in this application. Also, it is not a problem that only Tx is possible on the CC2340R5 in low data rate 2-FSK mode - as it will only be used as a transmitter. In this application, the CC2340R5 must only be able to Rx in BLE long-range and in 250kbps MSK with CC2500 whitening (which seems to be supported).  

    Therefore, I would like to know, when you mention "The PHY that you are asking for is not currently validated by TI and thus not provided in the SmartRF Studio 8 software.  This will update as validated PHYs are added to the CC2340RX device family" is this purely because they haven't been validated and tested by TI, or because the current SDK does not support it at all? If the former, and the SDK does support it theoretically, I would be happy to validate it myself. I just want to know what's actually possible before wasting any design time on things that aren't at all possible. 

    So, lastly I ask, can the rcl_settings_fsk_20_kbps_fec.h file be adjusted to 2.4kbps instead of 20kbps? Is there a certain field in any of the config structs within that header file which relate to the data rate? 

    Thank you

  • 0 in reply to Odhran Cummings
    TI__Guru**** 208457 points

    Hello Odhran,

    What Alex has provided is an example of custom PHY development outside of the typical and official validated/tested PHYs supported by Smart RF Studio 8 and the SimpleLink F3 SDK.  It shows that custom PHY creation is possible, but such efforts are not further carried by TI without establishing a critical business need.  We can provide some guidance towards your changes but 2 kbps is a very low data rate so I'm not sure whether it can dependably be achieved on a SimpleLink F3 device(i.e. uncharted territory).

    Regards,
    Ryan

  • 0 in reply to Ryan Brown1
    Prodigy 10 points

    Hi Ryan,

    I understand. That being the case, would it be possible for you to share some guidance on what changes to make in order to manipulate the data rate to be 2.4kbps and general guidance on how to create these custom PHYs? 

    I understand that they are official validated or tested and it's at my own discretion to validate any changes made - but it would be incredibly useful for me and no doubt to future customers who come across this thread.

    Thank you

  • 0 in reply to Odhran Cummings
    TI__Expert 8521 points

    Hello Odhran,

    Odhran Cummings said:
    share some guidance on what changes to make in order to manipulate the data rate to be 2.4kbps and general guidance on how to create these custom PHYs? 

    -For this we can do two things, first if you have the 7.40 F3 SDK downloaded you can locate one of the early versions of the PHY files found in (C:\ti\simplelink_lowpower_f3_sdk_7_20_01_10\source\ti\boards\cc23x0r5) (rcl_settings_fsk_20_kbps.c).

    -Second is for me to reach out to the internal team and ask how to change the RCL settings (some registers) to update the data rate, unlike the CC2500 which its very easy to update the data rate, the CC2340R5 is a bit more complex as it requires editing some files. 

    Odhran Cummings said:
    I understand that they are official validated or tested and it's at my own discretion to validate any changes made - but it would be incredibly useful for me and no doubt to future customers who come across this thread.

    -I believe the issue about validation had to do with no RX side existing on the CC2340R5, which made it difficult to validate, as well as the most recent changes I made not being validated at all (other than me testing CC2340R5 to CC2500).  

    Thanks,
    Alex F

  • 0 in reply to Alex Fager
    Prodigy 10 points

    Hi Alex,

    I can definitely look at the 7.40 F3 SDK for the early versions of the PHYs. However, as I am new to this SoC and not used to the file structure of the firmware, and since changing settings such as data rate is much more complex that expected, it would be great if you could also ask internally to the team for guidance on how to customise things such as datarate.

    Thank you in advance