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CC1125: Continuous transmission

Part Number: CC1125

continuous transmission.pdf

I would like to transmit continuously without breaks in the packet i.e. one continuous packet. Start and end of the transmission is under control of the user.

TXFIFO_THR is being used as an interrupt to signal when the TX FIFO has decreased to 7 bytes using GPIO 0.

GPIO 0  is connected to an oscilloscope. My first problem is that GPIO 0 always remains HIGH.

My second problem is that RF transmission appears to start but only for a very short time (perhaps one packet) then stops. I am using a spectrum analyser to see the RF output.

I have a TrxEB evaluation board. I can see continuous RF output when the evaluation board is set for Continuous TX. However, I can't seem to replicate Continuous TX on my own module.

P.S. On my own module, I have been able to transmit RF packets and have them successfully received by the TrxEB evaluation board so there is no hardware issue.

  • It is unclear to be what you are doing in your code, so I made a small example that demonstrates infinite packet length mode and the use of the FIFO threshold interrupt.

    I used SmartRF Studio to generate settings, and used the 2.4 kbps settings as a starting point, but change to infinite packet length mode, and set the FIFO threshold to 7:

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    static const registerSetting_t preferredSettings[]=
    {
    {CC112X_IOCFG3, 0xB0},
    {CC112X_IOCFG2, 0x06},
    {CC112X_IOCFG1, 0xB0},
    {CC112X_IOCFG0, 0x02},
    {CC112X_SYNC_CFG1, 0x0B},
    {CC112X_DEVIATION_M, 0xA3},
    {CC112X_MODCFG_DEV_E, 0x02},
    {CC112X_DCFILT_CFG, 0x1C},
    {CC112X_FREQ_IF_CFG, 0x33},
    {CC112X_IQIC, 0xC6},
    {CC112X_CHAN_BW, 0x19},
    {CC112X_MDMCFG0, 0x05},
    {CC112X_SYMBOL_RATE2, 0x5A},
    {CC112X_SYMBOL_RATE1, 0x36},
    {CC112X_SYMBOL_RATE0, 0xE3},
    {CC112X_AGC_REF, 0x20},
    {CC112X_AGC_CS_THR, 0x19},
    {CC112X_AGC_CFG1, 0xA9},
    {CC112X_AGC_CFG0, 0xCF},
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    My code example writs 122 bytes of 0xF5 to the TX FIFO and then strobe STX.

    Every time it gets a falling edge interrupt on GDO0 (less then 7 bytes in the TX FIFO), I write 122 new bytes of 0xF5

    At the receiver end I used SmartRF Studio and sync serial mode, and output the data on a pin to verify that my transmitter sent 0xF5 continuously

    Code:

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    void main(void) {
    // Initialize MCU and peripherals
    initMCU();
    // Write radio registers
    registerConfig();
    // Initialize packet buffer (sending an infinite packet with payload 0xF5)
    for (uint8 i = 0; i < PKTLEN; i++)
    txBuffer[i] = 0xF5;
    // Connect ISR function to GPIO0
    ioPinIntRegister(IO_PIN_PORT_1, GPIO0, &txFifoISR);
    // Interrupt on falling edge
    ioPinIntTypeSet(IO_PIN_PORT_1, GPIO0, IO_PIN_FALLING_EDGE);
    // Clear ISR flag
    ioPinIntClear(IO_PIN_PORT_1, GPIO0);
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Logic analyzer plots showing SPI + GDO0 on transmitter and received data and clock (serial mode) on the receiver (receiving 0xF5F5F5F5......)

    Siri

  • Thanks for your reply. There a some functions that you use i.e. cc112xSpiWriteTxFifo() and trxSpiCmdStrobe(CC112X_STX). Are these part of a TI CC112X library that is downloadable ? 

  • yes. I used the easylink example found here as a starting point:

    SWRC253 Code example or demo | TI.com

    Siri

  • These examples are for an msp430 uP. Not any good if you're using another type of uP. The CC1125 user guide is a bit confusing. It states that the FIFO depth is 128bytes. Yet in your example, CC112X_PKT_LEN = 0xFF which is 256 bytes.

    To be able to transfer data to the TX FIFO, the SPI comms must contain :-

    HEADER     0x3F (STANDARD_TX_FIFO_REG command). In reality, this will be 0x7E for burst mode write.

    ADDRESS   0x00 (address of the first FIFO register that contains the first data bytes)

    Followed by all of the payload bytes.

    If CC112X_PKT_LEN = 0xFF and the TX FIFO capacity is 0x7F, then how does the CC1125 know when the end of the packet has been reached ?

    What if I only want to transmit 5 bytes ? Does CC112X_PKT_LEN = 0x05 ?

  • The examples are written for the MCU that are on the kits that well sell.

    The only thing needed to port is the low-level SPI function. The data sent from the MCU to the CC1125 is the same no matter what MCU you are using.

    In your post you write that you want to implement Continuous transmission and in the example code you provide you have configured the radio for Infinite packet length mode, and in that case the PKT_LEN register is not used.

    This register is used in fixed packet length mode to determine how many bytes should be sent or received, or I variable packet length mode, to implement max packet length filtering in RX.

    In fixed or variable packet length mode, the MAX length is 255 bytes, as the PKT_LEN register is 8 bits wide.

    The fact that the RX FIFO is only 128 bytes long, simply means that if you want to send/receive packets longer than 128 bytes, you have to refill the TX FIFO or start reading the RX FIFO before the complete packet is sent/received. This is what the FIFO threshold interrupts can be used for.

    When using infinite packet length mode, the radio has no notion of the end of the packet (as there is not end of packet (it is infinite))

    How you implement TX and RX is different based on which packets you want to send (do they contain length info or not), are they shorter or longer than the FIFO size, are they shorter or longer than 255, are they infinite etc.

    To write your data to the TX FIFO you need to use Standard FIFO Access (if not, your FIFO pointers are not updated).

    That means that the first byte you send is 0x7F (burst write to address 0x3F), and the next byte is the first byte written to the FIFO.

    There are no headers (please see Table 3 in the user guide for details)

    If you want to send only 5 bytes, you DO NOT configure the radio for infinite packet length mode.

    You either use fixed packet length mode (set PKT_LEN = 5) and write your 5 payload bytes to the FIFO before strobing STX.

    If you use variable packet length mode, PKT_LEN is don’t care in TX, and you write the length byte (0x05) + the 5 payload bytes to the TX FIFO (in total 6 bytes must be written)

  • I am still uncertain how to store data in the TX FIFO. Here is a code snippet. It loads 15 bytes at a time into the TXFIFO. It does this 8 times (15bytes * 8 = 120bytes) then finally it loads 4 bytes in the TX FIFO.

    The FIFO_CFG register = 0x78 i.e. TXFIFO_THR = 120 bytes. 

    MODEM_STATUS0 register is read every time a packet of 15 bytes are loaded. The result of reading this register is always 0x00. I expected it to read 0x0C after the last 4 bytes are loaded.

    void Continuous_Mode(void)
    {
          volatile uint8_t index, result;

          txArray[0] = STANDARD_TX_FIFO_REG | BURST_MODE; //Burst mode.

          for(index = 1; index < SIZE_OF_TX_ARRAY; ++index) //Generate the data to be transmitted.
          {
                txArray[index] = 0xAC;
          }

          RF_SPI_Write(SFTX, 0x00, 0x00, SPI_TRANSACTION_TYPE_WRITE); //Flush the TX FIFO.

          for(index = 0; index < 8; ++index)
          {
                SPI_SpiUartPutArray(txArray, 16);         //Load 15 bytes into the TX FIFO.
                                                                               //i.e. 16 bytes - 1 byte (txArray[0] = STANDARD_TX_FIFO_REG | BURST_MODE)
                result = RF_SPI_Read(EXTENDED_REG, MODEM_STATUS0, SPI_TRANSACTION_TYPE_READ); //Read the TXFIFO status.
          }

         SPI_SpiUartPutArray(txArray, 5); //Load the last bytes into the TX FIFO.
         result = RF_SPI_Read(EXTENDED_REG, MODEM_STATUS0, SPI_TRANSACTION_TYPE_READ); //Read the TXFIFO status.
    }

  • I am still not sure I understand what exactly you are trying to do, but there are some misunderstandings regarding how the different registers behave, so I will at least explain them.

    When FIFO_CFG register = 0x78 (120), it means that the Threshold for the TX FIFO is 7 and that the Threshold for the RX FIFO is 128.

    This is explained in table 26 in the user guide.

    In MODEM_STATUS0 there are two signals you are looking for when writing to the FIFO:

    MODEM_STATUS0[3]:   TXFIFO_FULL

    Asserted when the TX FIFO is full. This means when there are 128 bytes in the TX FIFO. Not 124, like you are assuming

    MODEM_STATUS0[2]:   TXFIFO_THR

    Asserted when number of bytes is greater than or equal to the TX FIFO threshold. In our case, that will be when there are 7 or more bytes in the TX FIFO.

     

    That means that if you write 15 bytes 8 times to the TX FIFO, MODEM_STATUS0 will be 0x04 after the first 15 bytes have been written (asserted after 7 bytes).

    After writing 8 x 15 + 8 = 128 bytes to the TX FIFO, MODEM_STATUS0 will be 0x0C (There are 7 or more bytes in the TX FIFO, and it is also FULL).

    You can also read the NUM_TXBYTES register at this point, to see that you now have 128 bytes in the FIFO:

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    for(index = 0; index < 8; ++index)
    {
    // Write the 15 bytes in the txArray to the FIFO
    cc112xSpiWriteTxFifo(txArray, sizeof(txArray));
    cc112xSpiReadReg(CC112X_MODEM_STATUS0, &modemStatus0, 1);
    }
    // Write 8 bytes from txArray to fill up the FIFO (8 x 15) + 8 = 128
    cc112xSpiWriteTxFifo(txArray, 8);
    cc112xSpiReadReg(CC112X_MODEM_STATUS0, &modemStatus0, 1);
    cc112xSpiReadReg(CC112X_NUM_TXBYTES, &numTxBytes, 1);
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    All SPI traffic will look like this:

    Zooming in on the first 15 bytes being written + the reading of the MODEM_STATUS0 register, wee see that MODEM_STATUS0 = 0x04

    We can also see that FIFO_THR is asserted after 7 bytes written

    After writing 8 x 15 + 8 = 128 bytes to the TX FIFO, MODEM_STATUS0 will be 0x0C (There are 7 or more bytes in the TX FIFO, and it is also FULL).

    and NUM_TXBYTES will be 128 (0x80):

    Siri