I have been told by TI Support to ask my question here in the forum.
We plan to use CC120x wireless devices in a new project. From the RF point of view it
looks perfect. However, I have a question about the SPI connection in advance , because
we intend to use a FPGA instead of a MCU to control the device.
I would like to know the minimum intervention via SPI to be able to send and receive data.
We have to transmit and receive a fixed number of bytes (e.g. 24). A device normally
just sends a data packet and the receiver just receives these packets. Only occasionally
data flow is in the opposite direction.
Provided the RX and TX FIFO full/empty state is routed to a GPIO pin, is the device able to
start data transmission automatically if the payload has been written to the TX-FIFO?
Can next transmission easily be started again just by writing next data packet to the TX FIFO?
Same thing with the receiver. Is the RX able to get new packets right after reading out RX-FIFO?
I appreciate any information .
Thanks