TIDC-WL1837MOD-AUDIO-MULTIROOM-CAPE: PCM CLock jitter @ 2MHz ,BT as master

Huang Gaocheng

Prodigy 180 points

Part Number: TIDC-WL1837MOD-AUDIO-MULTIROOM-CAPE
Other Parts Discussed in Thread: WL1837

Hi, all

our customer used our module(WL1837), and configued the WL1837's BT as the master

if the PCM-CLK configued to 2MHz(or 1MHz), there is a jitter cr ossing with the PCM_CLK(on calling).

and if configued to 256KHz(or 512KHz),the PCM-CLK is OK.

The issue is the same when we used the TI’S WL1837 EVB(configued to 2048 and set loopback mode )

So if the PCM_CLK of WL1837 chipset can’t support the high frequence (>512KHz) when BT configured to be master?

or there are other reasons?

Expect your reply ,TKS

over 6 years ago

0 Chen Loewy over 6 years ago

TI__Expert 5285 points

Hello TKS,

i presume when you say we are master - that means Master on the PCM and not master in the connection.

I will check and see if i can find a HW expert - however why do you need to configure the PCM_CLK to 1-2Mhz?

Any specific reason?

BR,

Chen

0 Huang Gaocheng over 6 years ago in reply to Chen Loewy

Prodigy 180 points

Hi ,Loewy
TKS for reply . Yes ,you are right . Master is just on the PCM.
Our customers are using BT stack of the third Party which configure different BTS file according to customers's different requirements.
The PCM_CLK can support the Max 6MHz in the datasheet of WL1837, So one of our customer just uses the PCM_CLK 2Mhz
and find the issure.

0 Vincent Rodriguez over 6 years ago in reply to Huang Gaocheng

TI__Mastermind 28285 points

user5290702,

Can you provide the average Frequency across say a half second of clock cycles? Can you also provide the the frequency shift number you are seeing? Example: You seeing two frequencies, 2.1MHz and 1.9 MHz (This is Shifting back and forth by .2 MHz)

Thanks,

VR

0 Huang Gaocheng over 6 years ago in reply to Vincent Rodriguez

Prodigy 180 points

Hi, Vincent

we configured the PCM_clk to 256KHz on the TI'S 1837 EVB, there was a shift accrossing with the PCM_clk.

the Space is about 40nS however the PCM-clk configured to 2048KHz or 256KHz(128KHz).

So wthink there were some bugs in winlink chip-sets or the bits file and other .

the attachment show the measurent ,pls check

PCM-clock shift.xls

0 Huang Gaocheng over 6 years ago in reply to Chen Loewy

Prodigy 180 points

Hi Loewy
can you find a HW expert who can resolve the issure? TKS
the customer is expecting TI's reply

0 Vihang Parmar over 6 years ago in reply to Huang Gaocheng

TI__Mastermind 29250 points

Hi,

The PCM clock signal is generated from the WL18xx fast clock (26MHz on the WL183XMOD). Since either 2048kHz, 256kHz or 128kHz can not be generated by dividing the 26MHz fast clock, there might be a 1 fast clock cycle (~38.5nS) lag or lead once in a while to compensate for this.

Please see if you see the same behavior when setting the PCM clock to 1625kHz (1/16 * 26MHz) or 3250kHz (1/8 * 26MHz).

Best regards,
Vihang

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TIDC-WL1837MOD-AUDIO-MULTIROOM-CAPE: PCM CLock jitter @ 2MHz ,BT as master