Other Parts Discussed in Thread: CC3120, UNIFLASH
Hello.
Referring to the document SWPA230A – CC3120 and CC3220 SimpleLink™ Wi-Fi Embedded Programming, There are some things I am not clear on. And would like to get some information, rather that experiment with it and possibly brick it.
First, I have programmed the device using the 31XXEMUBOOST and Uniflash. All works as expected. However we will not be distributing thousands of these programmer boards and the uniflash application to customers nation wide. So the intent is to program it through the UART on the CC3120, using the above guide.
For initial deveopment, I am simply using a PC based program, and have communicated with the device as expected.
First, to program the device, I assume I use an output from Uniflash? There are four output files:
- BIN - Looks like a binary image of something in memory... This is just a direct image of the FLASH?
- HEX - ASCII representation, except this file is smaller (??!!)
- SLI - Another binary file, for the "image creator"
- UCF - Another binary file, used by the host
Am I supposed to download the UCF file via the UART through the CC3120 to have it program the FLASH RAM? Not the SLI?
Do these images also contain the files which I added using Uniflash? For example, the three /sys/cert/... files ? Or will those files have to be stored manually (for example, with the API via the SPI bus)?
Next, in document 230, section 5.2 there is a flowchart. However, in section 5.3 are the individual steps detailed in the flowchart.
Section 5.3.4 states:
To introduce some fixes to the ROM bootloader, it is necessary to download patches to the SRAM. The
procedure for getting information of SRAM storage follows:
(emphasis added) This states how to get info about the SRAM, but nothing describes anything about the "necessary to download patches..." What patches? What is the command to do so? It just just to section 5.3.5 Raw Storage Erase. If any "patches" are downloaded to the SRAM, they are erased in this step.
Section 5.3.7 again, says the "ROM is executed together with the programmed patches" What are the "patches"?
Section 5.3.10 explains that the SFLASH content must reside "in 8 bytes offset of block 33" . The content cannot fit in 8 bytes. This means it starts at the 8th byte of block 33, and continues linearly? There is NOT a need to perform an 8 byte offset at each block, only the first?
Is the image loaded in step 5.3.6 to load to SRAM the same as the image loaded in step 5.3.10 to load to SFLASH?
Conceptually, is it necessary to load the SRAM ir the SFLASH is also loaded? Logically, once the SFLASH is loaded, and the device is reset or power cycled, it would boot from the SFLASH, and the SRAM would be purged..?
As I develop more questions, I will follow up. Thanks.