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Part Number: WL1831MOD
Checking the signal integrity on SDIO (WiFi HCI) & UART (BT HCI) inputs of WL1381MOD, we found some over/undershoots of 0.5~0.6V above 1.8V = Vio. WIth 33R series res they are limited to 0.3V.
The datasheet is rather strict:
- absolute max values: VDD_IO for CLK_IN (SDIO clock) and VDD_IO+0.5V for other pins.
- recommended values: max Vih = VDD_IO
If we increase further the series res, we are afraid of degrading the rise time and get a not-steep-enough clock or data rise...
Question : is this 0.3V over/undershoot acceptable considering it is only a transient violation of the spec ? Could this really impact long term reliability of the WL1831 ?
Thanks a lot for your support
One more thing: we did not implement a series res on the signal connected to UART input BT_HCI_RX_1V8 and the over/undershoot is greater : ~0.7V.
The base of the triangle made by the overshoot is 6.5ns wide.
Question: if short violations are OK during over/undershoot, how much is acceptable ?
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In reply to THomas Hermans:
For the digital links, both SDIO and HCI/UART lines, the signa needs to be within the -0.5V to VIO + 0.5V. If you violate this there is potential damage that can occur within the device. These pins have ESD protection within the device and this has a potential to be triggered. We cannot guarantee reliability of the device it this is in violation.
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