CC2652P: Range only 5m

Thank you very much for your response.

1. We did not do conducted measurements yet.

2. Yes, we updated the firmware according to that.

void rfDriverCallback(RF_Handle client, RF_GlobalEvent events, void* arg)
{
    /* Switch off all paths first. Needs to be done anyway in every sub-case below. */
    GPIO_write(CONFIG_RF_HIGH_PA, 0);
    GPIO_write(CONFIG_RF_24GHZ, 0);

    if (events & RF_GlobalEventRadioSetup) {
        /* Decode the current PA configuration. */
        RF_TxPowerTable_PAType paType = (RF_TxPowerTable_PAType)RF_getTxPower(client).paType;

        /* 2.4 GHz */
        if (paType == RF_TxPowerTable_HighPA) {
            /* PA enable --> HIGH PA
         * LNA enable --> 2.4 GHz
         */
            GPIO_setMux(CONFIG_RF_24GHZ, IOC_PORT_RFC_GPO0);
            /* Note: RFC_GPO3 is a work-around because the RFC_GPO1 (PA enable signal) is sometimes not
                 de-asserted on CC1352 Rev A. */
            GPIO_setMux(CONFIG_RF_HIGH_PA, IOC_PORT_RFC_GPO3);
        } else {
            /* RF core active --> 2.4 GHz */
            GPIO_setMux(CONFIG_RF_24GHZ, IOC_PORT_GPIO);
            GPIO_setMux(CONFIG_RF_HIGH_PA, IOC_PORT_GPIO);
            GPIO_write(CONFIG_RF_24GHZ, 1);
        }
    } else {
        /* Reset the IO multiplexer to GPIO functionality */
        GPIO_setMux(CONFIG_RF_24GHZ, IOC_PORT_GPIO);
        GPIO_setMux(CONFIG_RF_HIGH_PA, IOC_PORT_GPIO);
    }
}


void rfDriverCallbackAntennaSwitching(RF_Handle client, RF_GlobalEvent events, void* arg)
{
    /* Nothing here as all the work happens in rfDriverCallback. */
}

3. I created some more labels to make it more clear. 

4. I turned of some labels, maybe it gives a better view now. I will rearrange components in the next PCB iteration to be as close as possible to the IC.

5. Layers below look like that:

6. It is based on CC1352PEM-XD7793-XD24-PA24.

7. I added the label, it's VDDS.

8. Yeah that looks like a mistake.

9. That one is part of the reference design.

OK, I see. Thanks for the updates.

I think it would be best to start by perrforming conducted measurements to make sure you're getting the expected power output based on the settings you apply. Without this step it's hard to do any debugging.

In addition, some immediate problems I see in the layout are:

1. I don't think it's feasible to achieve 50-ohm impedence on the RF path unless you have a very large gap between the top layer and the first inner layer. But it's very difficult to say without being able to measure and just from the screenshots. I would check with your board manufacturer to verify your geometry. I think that would generally cause range issues, but not the issue you're seeing where power settings don't change anything range-wsie.
2. 100 pF cap is for <1GHz path, would make sense to reduce this value to 47pF as per RF switch datasheet or 6.8pF only as per our reference design.
3. You should have blocking caps on both side of the switch as per our reference design and the switch datasheet, keep in mind for future revisions.
4. In general, if you're replicating the reference design and expect similar performance it's important to mirror all details. 
   1. For 20 dBm path you're missing a 1.6pF capacitor in the filter
   2. for 5 dBm the 1 pF is in the wrong place as noted above
   3. Taken together this would likely affect compliance as you may not be filtering harmonics sufficiently. Poor matches can also affect total output power which could cause range issue though.

-Jake

Hi Jake,

again, thank you for your effort. I reworked the design, it now follows the CC1352-P2 reference design.

I used a trace width of 0.293mm for the transmission lines because my PCB stackup looks like this:

My layers from top to bottom look like that:

The new schematic:

Any feedback is appreciated.

Hi Sebastian,

For the output match for the PCB antenna it should be something like:

either a PI or T filter. The important thing is to have the footprints for the components as the values will change depending on what's needed to properly match your antenna. Keep in mind that all three components would come after the 47pF DC block capacitor. Currently you have two components in series after the DC block.

For the layout on the RF path, I usually treat it as a co-planar waveguide for estimating:

So 'G' in the diagram above needs to be quite small. But again, this is all estimation, your best bet is to work with your board house as they have simulation tools based on their process and materials so that you can have a more accurate geometry.

Otherwise, it looks better.

-Jake

Hi Jake,

I copied that setup from the reference design. 

How much of the RF performance comes from antenna matching? Is it expected to work decent with those default values?