DRA648: J4(dra649) performance issue

Hi Joe,

Joe Shen said:

The default configuration is CPU@1Ghz + DRAM@400Mhz on J4, but we found the performance will increase 20% while using configuration CPU@900Mhz + DRAM@300Mhz.

It sounds not reasonable please also refer the attached file.

In the attached doc you have CPU loading/usage higher in CPU 1GHz/DDR 400MHz, thus you define that you have lower performance there?

Joe Shen said:

Is possible to measure the CPU clock on board(e.g. is there any hardware monitor pin which can be used to measure the CPU clock)?

No, we do not have such pin. You can dump MPU PLL registers or check mpu_ck through clock framework, see below e2e thread for details:

Joe Shen said:

Could you please guide us the register settings of CPU@1Ghz and CPU@900Mhz (e.g. MPU PLL settings + PMIC LDO settings)?

I will provide you example MPU PLL settings for CPU@1GHz and CPU@900MHz. Regarding PMIC settings, I think these should be the same for both 1GHz and 900MHz, as in both cases you should be in OPP166 1.35V. You can double check this in our PMIC e2e forum.

Joe Shen said:

Could you please guide us how to check the DRAM timing parameters is proper settings? Is there any tool which can be used ?

There is a ZIP flle (Centaurus_DDR3_Config_Instructions_v5.zip) inside the DRA64x CDDS folder. You will find there instructions regarding DDR3 configuration and software leveling.

Regards,
Pavel

For more info regarding performance see DM814x_DM810x_Performance.pdf available in the below link and also wiki page below:

e2e.ti.com/.../1303617

processors.wiki.ti.com/.../TI81XX_PSP_04.04.00.02_Feature_Performance_Guide

Joe Shen said:

Could you please guide us the register settings of CPU@1Ghz and CPU@900Mhz (e.g. MPU PLL settings

u-boot-2010.06 that comes with PSP 4.04.00.02 configured CPU for 600MHz, with the below settings:

MPUPLL_PWRCTRL/0x481C5048 = 0x0

MPUPLL_CLKCTRL/0x481C504C  = 0x0C11E819

MPUPLL_TENABLE/0x481C5050 = 0x0

MPUPLL_TENABLEDIV/0x481C5054 = 0x0

MPUPLL_M2NDIV/0x481C5058 = 0x00010001  (M2 = 1, N = 1)

MPUPLL_MN2DIV/0x481C505C = 0x0000003C (M = 60)

MPUPLL_FRACDIV/0x481C5060  = 0x0

MPUPLL_BWCTRL/0x481C5064 = 0x0

MPUPLL_FRACCTRL/0x481C5068 = 0x0

MPUPLL_STATUS/0x481C506C = 0x00000630

MPUPLL_M3DIV/0x481C5070 = 0x00000001

MPUPLL_RAMPCTRL/0x481C5074 = 0x0

The MPU PLL input clock (CLKINP) is 20MHz (DEV osc), the output clock is 600MHz:

CLKOUT = M/(N+1) * CLKINP * 1/M2 = 600MHz

For 900MHz and 1GHz you should only change M value (MPUPLL_MN2DIV):

for 900MHz, you should set M with 90 (MPUPLL_MN2DIV = 0x0000005A)

for 1Ghz, you should set M with 100 (MPUPLL_MN2DIV = 0x00000064)

Hi Pavel,

Thank you very much. I will do more tests.

Regards
Joe

Hi Pavel,

we have done more tests.
it shows the performance at CPU@1Ghz is lower than CPU@900Mhz.
after dump the MPU PLL registers we found the bit "HIGHJITTER" is set while setting CPU@1GHZ.

CPU @ 1000
# in32 0x481C5048
0x481c5048 : 0x00000000
# in32 0x481C504C
0x481c504c : 0x0411e809
# in32 0x481C5050
0x481c5050 : 0x00000000
# in32 0x481C5054
0x481c5054 : 0x00000000
# in32 0x481C5058
0x481c5058 : 0x00010001
# in32 0x481C505C
0x481c505c : 0x00000064
# in32 0x481C5060
0x481c5060 : 0x00000000
# in32 0x481C5064
0x481c5064 : 0x00000000
# in32 0x481C5068
0x481c5068 : 0x00000000
# in32 0x481C506C
0x481c506c : 0x00000632
# in32 0x481C5070
0x481c5070 : 0x00000001
# in32 0x481C5074
0x481c5074 : 0x00000000

we are trying to change the M,N value to check if there is improvement about this bit(highjitter).
Could you please give us some suggestions?

Regards
Joe

Hi Pavel,

we have tried different M/N/M2 parameters but the bit "HIGHJITTER" is always set to high while setting CPU@1GHz.
the performance on CPU@900Mhz increase around 30% than CPU@1Ghz, the DDR is the same clock 400Mhz.
Could you please suggest how to debug the next step?

Regards
Joe

Hi Pavel,

The performance test case is below:
-1-
the time of HMI display
-2-
check the loading of CPU after running application (BTA playback)

CPU@1Ghz CPU@900Mhz
-1- -1-
13 seconds 10 seconds
-2-
20% 14%

we think the "HIGHJITTER" is not the root cause.
please help to comment.

Regards
Joe

Joe Shen said:

we have done more tests.
it shows the performance at CPU@1Ghz is lower than CPU@900Mhz.

I would also suggest you to test with Audio playback/capture tests and EZSDK 5.05.02.00 Cortex-A8 ARM benchmark tests.

In the wiki page I have provided, DM814x TI EVM is tested with Audio playback/capture tests with ARM at 600Mhz and DDR3 at 400MHz.

The EZSDK benchmark tests are available at:

ti-ezsdk_dm814x-evm_5_05_02_00/example-applications/am-benchmarks-1.1

Joe Shen said:

after dump the MPU PLL registers we found the bit "HIGHJITTER" is set while setting CPU@1GHZ.

I see you have different NWELLTRIM value than what is used by default in DM814x EZSDK u-boot:

0x481c504c : 0x0411e809 - your value is 0x4

MPUPLL_CLKCTRL/0x481C504C  = 0x0C11E819 - in EZSDK u-boot the value is 0xC

Can you clarify from where you get the MPU PLL programming sequence? Can you try with 0xC in place of 0x4?

Make sure you are align with DRA64x Silicon Errata 3.0.5 DPLL_ARM: CortexTM-A8 MPU DPLL_ARM Reconfiguration Does Not Work

Check also your MPU PLL source clock (DEVOSC) is stable at aligned with DRA64x DM requirements:

8.4.1 Device (DEV) and Auxiliary (AUX) Clock Inputs

Check also your MPU PLL power supply is aligned with DRA64x DM requirements:

VDDA_ARM_PLL_1P8 has stable 1.8V

8.4.8.1 PLL Power Supply Filtering

Regards,
Pavel

Joe Shen said:

The performance test case is below:
-1-
the time of HMI display
-2-
check the loading of CPU after running application (BTA playback)

CPU@1Ghz CPU@900Mhz
-1- -1-
13 seconds 10 seconds
-2-
20% 14%

I would suggest two debug methods:

 - test your specific performance test on DM814x TI EVM and check how it goes there

- run audio and ARM benchmark tests on your DRA64x custom board and check how it goes

Regards,
Pavel

Hi Pavel,

Many thanks for your reply.
but customer is running QNX on DRA64x, Could you please share the benchmark tests on QNX?

Regards
Joe

Joe,

Unfortunately I am not familiar with QNX, I can help only for TI SDK. For QNX specific questions, you might check with QNX support team. See if the below QNX related links will be in help:

www.ti.com/.../embeddedsoftwarefulldetails.tsp
www.ti.com/.../companyfolder.tsp

community.qnx.com/.../TiDra6xxDm811x

Regards,
Pavel

Hi Pavel,

Many thanks for your help.

Regards
Joe

Hi Pavel,

After follow your suggestions to change the NWELLTRIM from 0x04 to 0x0C, the "HIGHJITTER" was gone.
CPU@1Ghz is better performance than CPU@900Mhz.
we did not find the detail descriptions about the NWELLTRIM.
Could you please share us the description of NWELLTRIM?

Regards
Joe

Hi Pavel,

thank you very much.

Regards
Joe

Hi

update more information.

When High jitter bit is set the Phraselock and Freqlock are assert to high
# in32 0x481C506C //MPUPLL_STATUS Register (offset = 6Ch)
0x481c506c : 0x00000632

we also try different M/N configurations but there is no one working well.
M N CLKINP M2 CLKOUT
100 1 20 1 1000
1000 4 20 4 1000
500 4 20 2 1000
2000 4 20 8 1000
200 1 20 2 1000

Regards
Joe

Hi Joe,

Just to let you know that answers may delay as Pavel is OoO

Best regards
Lucy

Lucy,
We're investigating the suggested answer at this time.
John

Joe Shen said:

update more information.

When High jitter bit is set the Phraselock and Freqlock are assert to high
# in32 0x481C506C //MPUPLL_STATUS Register (offset = 6Ch)
0x481c506c : 0x00000632

we also try different M/N configurations but there is no one working well.
M N CLKINP M2 CLKOUT
100 1 20 1 1000
1000 4 20 4 1000
500 4 20 2 1000
2000 4 20 8 1000
200 1 20 2 1000

Joe,

What is the question here? Can you provide more details about what exactly you need to know?

Regards,
Pavel

Hi Pavel,

Could you please give us the sequence how to disable MPU_PLL. we try to set the TRIM value on the fly. if we adjust the MPU parameters to find the HIGHJITTER bit active, we want to disable MPU_PLL and set again.

I did not find the disable sequence in GEL file or in u-boot.

Regards

Joe

 

Joe,

You need to first put MPU PLL in idle bypass mode. See the below e2e threads for more info regarding programming sequence of a PLL:

e2e.ti.com/.../936658
e2e.ti.com/.../332682

Regards,
Pavel

Hi Pavel,

thanks, i will call the function PLL_Clocks_Config in GEL file
it is include bypass mode setting

WR_MEM_32(Base_Address+CLKCTRL, RD_MEM_32(Base_Address+CLKCTRL)|0x00800000);
while (( (RD_MEM_32(Base_Address+STATUS)) & 0x00000101) != 0x00000101);
WR_MEM_32(Base_Address+CLKCTRL, RD_MEM_32(Base_Address+CLKCTRL)& 0xfffffffe);

Regards
Joe

Hi Pavel,

I use the GEL file to config the A8_PLL please help to check.

-1-

use the default GEL file to config CPU@1GHz

N,M,M2 = 1,100,1

A8PLL_CLKCTRL = 0x0411E809

A8_PLL_Config(UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2)
{
UWORD32 rval_ctrl,ref_clk,clk_out = 0;
UWORD32 m2nval,mn2val = 0;
ref_clk = CLKIN/(N+1);
clk_out = (ref_clk*M)/M2;

m2nval = (M2<<16) | N; //need to check the bit position of M2
mn2val = M;
WR_MEM_32(A8PLL_M2NDIV ,m2nval);
WR_MEM_32(A8PLL_MN2DIV ,mn2val);
WR_MEM_32(A8PLL_TENABLEDIV ,0x1);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLEDIV ,0x0);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLE ,0x1);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLE ,0x0);
wait_delay(3);
rval_ctrl = RD_MEM_32(A8PLL_CLKCTRL);
WR_MEM_32(A8PLL_CLKCTRL,(rval_ctrl & 0xff7fffff) | 0x1);
while (( (RD_MEM_32(A8PLL_STATUS)) & 0x00000600) != 0x00000600);
wait_delay(10);
CLKOUT = clk_out;

}

but it will get highjitter (A8PLL_STATUS 0x0x00000632)

-2-

put MPU PLL in idle bypass mode first then using the same control value (A8PLL_CLKCTRL = 0x0411E809)

N,M,M2 = 1,100,1

A8_PLL_Config(UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2)
{
UWORD32 rval_ctrl,ref_clk,clk_out = 0;
UWORD32 m2nval,mn2val = 0;
ref_clk = CLKIN/(N+1);
clk_out = (ref_clk*M)/M2;

WR_MEM_32(A8PLL_CLKCTRL, RD_MEM_32(A8PLL_CLKCTRL)|0x00800000);
while (( (RD_MEM_32(A8PLL_STATUS)) & 0x00000101) != 0x00000101);
WR_MEM_32(A8PLL_CLKCTRL, RD_MEM_32(A8PLL_CLKCTRL)& 0xfffffffe);

m2nval = (M2<<16) | N; //need to check the bit position of M2
mn2val = M;
WR_MEM_32(A8PLL_M2NDIV ,m2nval);
WR_MEM_32(A8PLL_MN2DIV ,mn2val);
WR_MEM_32(A8PLL_TENABLEDIV ,0x1);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLEDIV ,0x0);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLE ,0x1);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLE ,0x0);
wait_delay(3);
rval_ctrl = RD_MEM_32(A8PLL_CLKCTRL);
GEL_TextOut("\tA8PLL_CLKCTRL 0x%x \n",,,,,rval_ctrl);

WR_MEM_32(A8PLL_CLKCTRL,0x0411E809);
while (( (RD_MEM_32(A8PLL_STATUS)) & 0x00000600) != 0x00000600);
wait_delay(10);
CLKOUT = clk_out;
GEL_TextOut("\tA8PLL_STATUS 0x%x \n",,,,,RD_MEM_32(A8PLL_STATUS));

}

CortexA8: Output: **** DM8148 MPU ADPLL INIT IS in Progress .........
CortexA8: GEL Output: A8PLL_CLKCTRL 0x0x0491E808
CortexA8: GEL Output: A8PLL_STATUS 0x0x00000630
CortexA8: GEL Output: A8 ADPLLJ CLKOUT value is = 1000

the highjitter is gone, Could you please help to check the sequence 2.

Regards

Joe

Joe Shen said:

I use the GEL file to config the A8_PLL please help to check.

Which GEL file exactly you are using?

Joe Shen said:

-1-

use the default GEL file to config CPU@1GHz

N,M,M2 = 1,100,1

A8PLL_CLKCTRL = 0x0411E809

A8_PLL_Config(UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2)
{
UWORD32 rval_ctrl,ref_clk,clk_out = 0;
UWORD32 m2nval,mn2val = 0;
ref_clk = CLKIN/(N+1);
clk_out = (ref_clk*M)/M2;

m2nval = (M2<<16) | N; //need to check the bit position of M2
mn2val = M;
WR_MEM_32(A8PLL_M2NDIV ,m2nval);
WR_MEM_32(A8PLL_MN2DIV ,mn2val);
WR_MEM_32(A8PLL_TENABLEDIV ,0x1);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLEDIV ,0x0);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLE ,0x1);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLE ,0x0);
wait_delay(3);
rval_ctrl = RD_MEM_32(A8PLL_CLKCTRL);
WR_MEM_32(A8PLL_CLKCTRL,(rval_ctrl & 0xff7fffff) | 0x1);
while (( (RD_MEM_32(A8PLL_STATUS)) & 0x00000600) != 0x00000600);
wait_delay(10);
CLKOUT = clk_out;

}

but it will get highjitter (A8PLL_STATUS 0x0x00000632)

Note that this GEL file function is used during device boot up, not on the fly. Here in this case, MPU PLL is in idle mode by default.

The high jitter is caused by A8PLL_CLKCTRL value, NEWTRIM is 0x4 and bit 4 should be 1 (reset value).

Joe Shen said:

-2-

put MPU PLL in idle bypass mode first then using the same control value (A8PLL_CLKCTRL = 0x0411E809)

N,M,M2 = 1,100,1

A8_PLL_Config(UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2)
{
UWORD32 rval_ctrl,ref_clk,clk_out = 0;
UWORD32 m2nval,mn2val = 0;
ref_clk = CLKIN/(N+1);
clk_out = (ref_clk*M)/M2;

WR_MEM_32(A8PLL_CLKCTRL, RD_MEM_32(A8PLL_CLKCTRL)|0x00800000);
while (( (RD_MEM_32(A8PLL_STATUS)) & 0x00000101) != 0x00000101);
WR_MEM_32(A8PLL_CLKCTRL, RD_MEM_32(A8PLL_CLKCTRL)& 0xfffffffe);

m2nval = (M2<<16) | N; //need to check the bit position of M2
mn2val = M;
WR_MEM_32(A8PLL_M2NDIV ,m2nval);
WR_MEM_32(A8PLL_MN2DIV ,mn2val);
WR_MEM_32(A8PLL_TENABLEDIV ,0x1);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLEDIV ,0x0);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLE ,0x1);
wait_delay(3);
WR_MEM_32(A8PLL_TENABLE ,0x0);
wait_delay(3);
rval_ctrl = RD_MEM_32(A8PLL_CLKCTRL);
GEL_TextOut("\tA8PLL_CLKCTRL 0x%x \n",,,,,rval_ctrl);

WR_MEM_32(A8PLL_CLKCTRL,0x0411E809);
while (( (RD_MEM_32(A8PLL_STATUS)) & 0x00000600) != 0x00000600);
wait_delay(10);
CLKOUT = clk_out;
GEL_TextOut("\tA8PLL_STATUS 0x%x \n",,,,,RD_MEM_32(A8PLL_STATUS));

}

CortexA8: Output: **** DM8148 MPU ADPLL INIT IS in Progress .........
CortexA8: GEL Output: A8PLL_CLKCTRL 0x0x0491E808
CortexA8: GEL Output: A8PLL_STATUS 0x0x00000630
CortexA8: GEL Output: A8 ADPLLJ CLKOUT value is = 1000

the highjitter is gone, Could you please help to check the sequence 2.

Looks correct when making changes on the fly. Only CLKCTRL value might cause problems, see my comment above regarding CLKCTRL value.

Regards,
Pavel

Hi Pavel,

I am using "ccsv7\ccs_base\emulation\boards\dm814x_evm\gel\DM8148_EVM.gel" file to do this test.
there is no software in emmc. I did the 2 cases in below step separately.

- power off and power on device
- attach the MPU and load the GEL file
- running "DM8148 INDIVIDUAL PLL Config -> MPU_PLLCONFIG"

Regards
Joe

Joe Shen said:

I am using "ccsv7\ccs_base\emulation\boards\dm814x_evm\gel\DM8148_EVM.gel" file to do this test.
there is no software in emmc. I did the 2 cases in below step separately.

- power off and power on device
- attach the MPU and load the GEL file
- running "DM8148 INDIVIDUAL PLL Config -> MPU_PLLCONFIG"

This looks to be correct