TDA3: QSPI/McSPI AC timing

Hi Kenshow,

Measuring the signal is normally done at active to active point, i.e. if your active clock edge is rising it is good starting from 90% VDD, if it is falling - 10%VDD. Same is valid for the target signal. It is not common practice to measure on 50% of the signal, as normally this is not a valid signal level, but in general you should get the same result.

For the second one - my understanding is SS6 should be Delay time, spi_sclk active edge to mcspi_somi end of transition; and spi_sclk active edge to mcspi_somi start of transition should be defined as hold time. Or at least this is the way defined in QSPI diagram.
I am currently waiting the spec-owner to confirm for McSPI diagram.

Thanks,
Dian

Kenshow,

1) As long as you measure from equal points, you should get the same result (including 50% level). Note that the data manual do not include delays by board routes. I'll try to push on approving/adding this information in DM.

2) The feedback is that SS6 defines both the min and max delay time in a single parameter. Min value is to start of inactive period and max is to end of it. The diagrams for McSPI will be updated in the DM to remove gray invalid periods.

Thanks,
Dian

Hi Kenshow,

Yes, all rise and fall times are calculated for 10% to 90% of VDDS. All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDDI/O)/2. The default SLEWCONTROL settings in each pad configuration register must be used to guaranteed timings, unless specific instructions otherwise are given in the individual timing sub-sections of the data manual. All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns). The timing parameter values specified in the data manual do not include delays by board routes. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences.

Thanks,
Dian