PROCESSOR-SDK-TDAX: Sending 24-bit data from TDA2x VOUT to TDA2x VIN

Hi Bosko,

I have forwarded your question to ISS expert.

Regards,
Yordan

Hi Bosko,

Are you getting callbacks from the VIP? If so,
I hope you have taken care of pin-mux and polarity (especially the vSync).
Also, are you using TI Evaluation Board?

Regards,
Sujith

Hello Sujith,

We use our board that is equiped with TDA2x chips. VOUT1 on TX chip is connected to VIN1A on RX chip and TX should send 24-bit data. Problem is that TX chip only sends 8-bits of data, and that is blue component. On RX side, pInstPrm->videoIfWidth is set to SYSTEM_VIFW_24BIT. Picture that I see on screen is fine, but it only has blue component. In bsp_boardTda2xx.c pinmuxes are already set with Bsp_platformSetPinmuxRegs(). First parameter is set to 0, second parameter is register name and third parameter is BSP_PLATFORM_IOPAD_CFG_DEFAULT. That seems to be fine.

Regards,
Bosko

Hello Brijesh,

I set pinmuxes in usecases, using Bsp_platformSetPinmuxRegs() function. On TX side, as first parameter I set 0, second parameter is register name and third parameter is BSP_PLATFORM_IOPAD_CFG_DEFAULT. On RX side, first parameter is 0, second is register name and third BSP_PLATFORM_IOPAD_CFG_INPUTENABLE_BI. Before I set pinmuxes on RX side, values in registers were 0x40000 for CLK, FLD, DE, HSYNC, VSYNC and data registers from D0 to D7 and 0x4000f for D8 to D23. Now, after setting pinmuxes for VIN, all values in data registers are 0x40000. On TX side, all registers have already been set to 0x40000, but I still have the same behavior.

Best regards,

Bosko

Hi Bosko,

can you dump VIP registers and share me? i think it starts from 0x48975500. can you dump 50 registers from this address.

Rgds,
Brijesh

Hello Brijesh,

Here are the registers and their values.

TX side:
0x48975500 0x0
0x48975504 0x0
0x48975508 0x0
0x4897550C 0x0
0x48975510 0x0
0x48975514 0x3ffedf
0x48975518 0x3ffedf
0x4897551C 0x0
0x48975520 0xffffffff
0x48975524 0xffffffff
0x48975528 0xffffffff
0x4897552C 0xffffffff
0x48975530 0x0
0x48975534 0x0
0x48975538 0x0
0x4897553C 0x0
0x48975540 0x0
0x48975544 0x0
0x48975548 0x0
0x4897554C 0x0
0x48975550 0x0
0x48975554 0x0
0x48975558 0x0
0x4897555C 0x0
0x48975560 0x0
0x48975564 0x0
0x48975568 0x0
0x4897556C 0x0
0x48975570 0x0
0x4897557  0x0
0x48975578 0x0
0x4897557C 0x0
0x48975580 0x0
0x48975584 0x0
0x48975588 0x0
0x4897558C 0x0
0x48975590 0x0
0x48975594 0x0
0x48975598 0x0
0x4897559C 0x0
0x489755A0 0x0
0x489755A4 0x0
0x489755A8 0x0
0x489755AC 0x0
0x489755B0 0x0
0x489755B4 0x0
0x489755B8 0x0
0x489755BC 0x0
0x489755C0 0x0
0x489755C4 0x0
0x489755C8 0x0

RX side:
0x48975500 0x0
0x48975504 0x40b904
0x48975508 0x5000320
0x4897550C 0x0
0x48975510 0x0
0x48975514 0x3ffedf
0x48975518 0x3ffedf
0x4897551C 0x0
0x48975520 0xffffffff
0x48975524 0xffffffff
0x48975528 0xffffffff
0x4897552C 0xffffffff
0x48975530 0x5000000
0x48975534 0x0
0x48975538 0x0
0x4897553C 0x0
0x48975540 0x0
0x48975544 0x0
0x48975548 0x0
0x4897554C 0x0
0x48975550 0x0
0x48975554 0x0
0x48975558 0x0
0x4897555C 0x0
0x48975560 0x0
0x48975564 0x0
0x48975568 0x0
0x4897556C 0x0
0x48975570 0x0
0x48975574 0x0
0x48975578 0x0
0x4897557C 0x0
0x48975580 0x0
0x48975584 0x0
0x48975588 0x0
0x4897558C 0x0
0x48975590 0x0
0x48975594 0x0
0x48975598 0x0
0x4897559C 0x0
0x489755A0 0x0
0x489755A4 0x0
0x489755A8 0x0
0x489755AC 0x0
0x489755B0 0x0
0x489755B4 0x0
0x489755B8 0x0
0x489755BC 0x0
0x489755C0 0x5008000
0x489755C4 0x3200000
0x489755C8 0x0

Best regards,

Bosko

Hi Bosko,

The input is ok, but the interface type is set to discrete sync single 4:2:2 YUV stream in the register 0x48975504 0x40b904, the value in the last nibble is 4, but it should be set to 0xA for discrete sync single channel 24bit RGB input. can you please try with this?

Rgds,
Brijesh

Hi Brijesh,

I have tried with setting 0x48975504 register to 0x40b90A in fvid2_drvMgr.c file, in Fvid2_control function after call of controlFxn function. When I read register value after, it is set to 0x40b90A, it does not change. But after writing that value in register I get just black picture on HDMI.

Best regards,

Bosko

Hi Bosko,

but after changing this register value, do you see correct frame size in the 0x48975530 register offset? If it is, then VIP is detecting correct stream. You could try dumping one of the captured frame and see if it looks correct?.

Rgds,
Brijesh

Hi Brijesh,

After setting register 0x48975504 value, I get 0x0 in 0x48975530, but before setting the value I get 0x5000000. I think that problem may be with sending side, it is like it is only sending first 8-bits. I set 24-bit data pVInfo->vencOutputInfo.videoIfWidth = SYSTEM_VIFW_24BIT like this in ChainsCommon_DualDisplay_StartDisplayCtrl function. Is there maybe another place where it needs to be set?

Best regards,
Bosko

Hi Brijesh,

I set pinmuxes in use case main function this way: Bsp_platformSetPinmuxRegs((UInt32) 0, (UInt32) CTRL_CORE_PAD_VIN1A_VSYNC0, BSP_PLATFORM_IOPAD_CFG_DEFAULT), tha same on output of first SoC, just changed second parameter of the function. When I print the value of 0x4A0034F0 register before call of Bsp_platformSetPinmuxRegs function I get 0x40000f value, and after call of function it is set to 0x400000. It seems ok to me. Can we have a session, maybe via TeamViewer?

Best regards,
Bosko

Hi Bosko,

Not only just one pin, can you check all the pinmux values? Also can you probe the signal out of DSS and see if they are coming out? 

Also probe the sync signals at the VIP port and see if they are coming in?

Regards,

Brijesh

Hi Brijesh,

Before setting pinmuxes values are 0x4000f for VOUT1_CLK, VOUT1_DE, VOUT1_FLD, VOUT1_HSYNC, VOUT1_VSYNC and VOUT1_Dx, and for VIN1A_CLK0, VINA1_DE0, VIN1A_FLD0, VIN1A_HSYNC0, VIN1A_VSYNC0 and VIN1A_Dx, and after setting pinmuxes it is 0x40000. I probed signal on DSS, only first 8 lines are active, other 16 are not. On VIP the same situation. Output port is directly connected on input port.

Can we have a TeamViewer session, if you could just take a look on what has been done, I will prepare the environment?

Best regards,

Bosko

Hi Bosko,

oh that means dss is not outputting on all 24 lines, something to do with the dss configuration. Did you check the pinmux for the VOUT1_D0 to VOUT_D24 data lines? Also can you please share the DSS register dump when it is running?

Rgds,
Brijesh

Hi Brijesh,

Yes, I checked the pinmuxes for the VOUT1_D0 to VOUT_D24, seems fine to me. Value of those registers is 0x40000. I found registers on 0x58000000 address, with value 0x61 on both sides, 0x58000014 with 0x1 value on both sides, 0x58000040 with 0x10001 on transmitting side and 0x10000 on receiving side and 0x5800005C with value 0x1408a82 on transmitting side and 0x1408a81 on receiving side. Is that ok?

Regards,
Bosko

Hi Bosko,

Sorry for the late reply. If the pinmux looks correct and probing says that only lower 8bit have valid data, it means DSS is not configured correctly. Could you please share the DSS register dump?

Regards,

Brijesh

Hi Brijesh,


Register on 0x58000000 address has value 0x61 on receiving and transmitting side, register 0x58000014 has value 0x1 on both sides, 0x58000040 with 0x10001 on transmitting and 0x10000 on receiving side and register 0x5800005C has value 0x1408a82 on transmitting and 0x1408a81 on receiving side.

Best regards,
Bosko

Bosko,

DISPC Base address is 0x58001000 and i require register values for the VP output, ie CONTRO/CONFIG/SIZE/TIMING/POL_FREQ//DATA_CYCLE  registers of DPSPC.

Rgds,

Brijesh

Hi Brijesh,

On transmitting side register values are:
0x58001040 CONTROL1 0x90034b
0x58001238 CONTROL2 0x300
0x58001848 CONTROL3 0x300
0x58001044 CONFGI1 0x3c04
0x58001044 CONFGI2 0x0
0x58001044 CONFGI3 0x0
0x58001064 TIMING_H1 0x9f05f7b
0x58001068 TIMING_V1 0xc00622
0x58001064 TIMING_H2 0x0
0x58001068 TIMING_V2 0x0
0x58001064 TIMING_H3 0x0
0x58001068 TIMING_V3 0x0
0x5800107C SIZE LCD1 0x31f04ff
0x5800106C POL FREQ1 0x7000
0x58001408 POL FREQ2 0x0
0x5800183C POL FREQ3 0x0
0x580011D4 DATA1 CYCLE1 0x8
0x580011D8 DATA1 CYCLE2 0x8
0x580011Dc DATA1 CYCLE3 0x8
0x580013c0 DATA2 CYCLE1 0x0
0x580013c4 DATA2 CYCLE2 0x0
0x580013c8 DATA2 CYCLE3 0x0
0x58001828 DATA3 CYCLE1 0x0
0x5800182c DATA3 CYCLE2 0x0
0x58001830 DATA3 CYCLE3 0x0
0x580010C8 VID1 SIZE 0x31f04ff
0x58001158 VID2 SIZE 0x31f04ff
0x580013A8 VID3 SIZE 0x0

and on receiving side are:

0x58001040 CONTROL1 0x342
0x58001238 CONTROL2 0x300
0x58001848 CONTROL3 0x300
0x58001044 CONFGI1 0x3004
0x58001044 CONFGI2 0x0
0x58001044 CONFGI3 0x0
0x58001064 TIMING_H1 0x0
0x58001068 TIMING_V1 0x0
0x58001064 TIMING_H2 0x0
0x58001068 TIMING_V2 0x0
0x58001064 TIMING_H3 0x0
0x58001068 TIMING_V3 0x0
0x5800107C SIZE LCD1 0x0
0x5800106C POL FREQ1 0x0
0x58001408 POL FREQ2 0x0
0x5800183C POL FREQ3 0x0
0x580011D4 DATA1 CYCLE1 0x0
0x580011D8 DATA1 CYCLE2 0x0
0x580011Dc DATA1 CYCLE3 0x0
0x580013c0 DATA2 CYCLE1 0x0
0x580013c4 DATA2 CYCLE2 0x0
0x580013c8 DATA2 CYCLE3 0x0
0x58001828 DATA3 CYCLE1 0x0
0x5800182c DATA3 CYCLE2 0x0
0x58001830 DATA3 CYCLE3 0x0
0x580010C8 VID1 SIZE 0x31f04ff
0x58001158 VID2 SIZE 0x0
0x580013A8 VID3 SIZE 0x0

On VOUT value of data, clk, de, fld hsync and vsync registers is 0x40000.

Regards,
Bosko

Hi Brijesh,

TDM was the problem. Now I get 24-bit on output. Thank you very much.

Best regards,
Bosko