AM335x Pin Muxing

Hi,

Can you please help answer the questions below regarding the AM335x pin muxing:

I am confused regarding pin assignments with the AM335X. I want to use Non-multiplexed mode with the address and data lines on the AM3352. But certain pins, such as address A3 for example are available on two different pins.

 The following shots (attached) are from the AM335X TI Pin Muxing Tool.

 Notice below GPMC A1 MUX 0 and GPMC A16 MUX0. These are the same pin, but the device muxes A0 and A16 on the same pin.

 (See attached)

Now, notice GPMC_A0_MUX1.

 (See attached)

 I can’t find any documentation showing what MUX0 and MUX1 mean. Maybe they are just labels. Since I am using Non-multiplexed mode I am wondering which sets of pins I should use for the address bus. Maybe it doesn’t matter, but I want to choose the set that will work or make more sense. I am intending on using a 16 bit SRAM like device and a 16 bit NAND FLASH on the same bus.

4812.AM335X Pin MUX.docx

Thanks,

Andrea

  • The AM335x device contains many peripheral interfaces. In order to reduce package size and cost while maintaining maximum functionality, many of the AM335x terminals can multiplex up to eight signal functions.  However, this may impose significant limitations on the number of peripherals and peripheral functions available concurrently.

    Many of the AM335x peripheral inputs and output signals were multiplexed to more than one device terminal as a way to reduce the limitations of pin-multiplexing.  Multiplexing signals to multiple terminals adds a significant design complexity because each signal path needs to be properly timed with all other signals of the associated peripheral interface.  If several signals of a peripheral interface can be multiplexed to multiple terminals, the number of possible combinations can be large.  This makes it prohibitive to close timing on all possible combinations.  Therefore, the AM335x does not support all possible combinations of pin-multiplexing.  The supported combinations of pin-multiplexing for a specific peripheral interface are referred to as valid IO Sets.

    The Pin Mux Utility was developed to help system designers select the appropriate pin-multiplexing configuration for their AM335x based product design.  This tool provides a way to select valid IO Sets of specific peripheral interfaces to insure the pin-multiplexing configuration selected for a design only uses valid IO Sets supported by AM335x.

    In some cases there may be another level of pin multiplexing in the peripheral module.  For example, the GPMC AD[15:0] signals are multiplexed between address outputs and data inputs/outputs by logic in the GPMC module.  See the GPMC Pin Multiplexing Options table in the GPMC section of the AM335x TRM for more information.   The first level of multiplexing in meant to be a static configuration based on PCB connections.  The GPMC A0 Mux0 and GPMC A0 Mux1 signal names represent two possible paths that can be used to route the GPMC A0 signal to pins.  However, you need to make sure the combination of pin multiplexing for the respective peripheral signals is one of the valid IO Sets defined in the Pin Mux Utility.

    Regards,
    Paul

  • In reply to peaves:

    I am attaching my pin mux utility file.  I think it is error free but it would really help if I could get verification of that.

     

    The concern I have is not the “muxability” but more software related, does the processor boot out of NAND and give us the opportunity to really set up all the muxing and the address and  data bus or is something locked in at bootup that may cause a bootup concern?

     

    8311.PinMuxDesignState_AM3352ZCZ.zip

  • In reply to Frank D'Aliesio:

    Frank:

    No problems with the pin mux data file you attached.

    The ROM boot loader takes care of booting from NAND as long as it is a supported NAND device

    and the SYSBOOT pins are set as needed after reset.  U-Boot code then configures pin muxing.

    The u-boot code may need to be customized relative to the settings we use for the TI EVM.

    Regards,

    Michael T

  • In reply to Michael T:

    Hi Michael,

    Hope you could help me here.

    I am going through the chapter 26 on Boot modes, so I can verify my final pin muxing setup with the boot pin allocation.

    I have a problem with the NOR boot mode, which can be selected as MUX1 or MUX2 mode.

    Looking at table 26.9 and the pin mux utility, I can only see very little correlation.

    Q1: What does XIP_MUX1 and MUX2 represent?  

    It does not seem to match with Mode 0-7, and the pin name MUX  comments don’t match either.

    I can see some possible matches of the mux naming on the ZCE package (pin mux utility) but MUX2 ???  

    Q2:   In table 26.9 some signals are in bold, what does that mean?

    Could you please try to clarify?  Thanks in advance.