AM335x RMII Interface.

Hi,

I'm working on similar project. Did you have success?

Hi,

      first i used the u-boot from the ti web. in that u-boot i made it working.

Currently i am working on latest u-boot from the git.

Regards

Shyam

Hi,

Actually I'm working with different phy (DP83848) but the interface is RMII with 50MHz ref_clk. I had  little succes afterwards I had tried lots of things. I changed static struct cpsw_slave_data cpsw_slaves[0].phy_id = 1 and static struct cpsw_slave_data cpsw_slaves[1].phy_id = 0 lastly. Now phy is working but sometime it has unstable behaviour.

do you know if there is a phy specific codes for rmii interfaced phys?

Are you trying to use the AM335x to source the 50MHz RMII reference clock?  If so , this is will not work.  Please read Advisory  1.0.16 in the AM335x Silicon Errata.

Regards,
Paul

If you force the rmii-phy in 10mbps (clock generated by SOC), the link is stable (micrel KSZ8021)

We tried with 20 different link partners so far, and they set up a reliable link.

For most applications 10mbps is fast enough.

Best Regards,

Wim

Thank you, Yes I'm working with RMII reference clock. I have read the advisory and it says rmii_refclk jitter is very high. Our requirements is +/-50ppm so I measured the frequency of ref_clk, It seems sufficient. OK I'II try external clock for 100Mbps and current clock for 10Mbps.

Hi,

You are right, it is stable at 10Mbps. Thank you all.

Hi,

I'm working on a project under Linux with AM335x processor. 

I unfortunetaly tried to configure the link to 10Mbps.

How do you succed ?

1-u-boot configuration ?

2-Kernel patch ?

I used a DP83848 phy.

Thanks by advance

Hi,

There is no any kernel or uboot patch. Firstly you have to configure pin mux correctly then if you use rmii interface with ref_clk you should force phy to 10Mbps for uboot and kernel. In uboot source you have to select which interface you use in the gmii_sel register. Lastly your physical addres is important you must set it in slave_data correctly.

Hello Guys,

I'm also using the AM3354 device with DP83848, I'm using the MII interface and hence not using the REF CLK. I can get auto negotiation to happen, but when I try dhcp I get the following:

link up on port 0, speed 100, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3

And this continues till broadcast 10 and then starts retry. I've confirmed that I can read the PHY ID and other PHY registers. My pin mux is defined as follows:

static struct module_pin_mux mii1_pin_mux[] = {
    {OFFSET(mii1_crs), MODE(0) | RXACTIVE},     /* MII1_CRS */
    {OFFSET(mii1_col), MODE(0) | RXACTIVE},     /* MII1_COL */
    {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},    /* MII1_RXERR */
    {OFFSET(mii1_txen), MODE(0)},                /* MII1_TXEN */
    {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},    /* MII1_RXDV */
    {OFFSET(mii1_txd3), MODE(0)},                /* MII1_TXD3 */
    {OFFSET(mii1_txd2), MODE(0)},                /* MII1_TXD2 */
    {OFFSET(mii1_txd1), MODE(0)},                /* MII1_TXD1 */
    {OFFSET(mii1_txd0), MODE(0)},                /* MII1_TXD0 */
    {OFFSET(mii1_txclk), MODE(0) | RXACTIVE},    /* MII1_TXCLK */
    {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},    /* MII1_RXCLK */
    {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},    /* MII1_RXD3 */
    {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},    /* MII1_RXD2 */
    {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},    /* MII1_RXD1 */
    {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},    /* MII1_RXD0 */
    {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
    {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},    /* MDIO_CLK */
    {-1},
};

Any ideas or thoughts on where the problem can be??

Regards

Santhosh

When the DP83848 is configured for MDIO address 0x0 it defaults to MII isolate mode.  The MII can be brought out of isolate mode by writing to a device specific MDIO register.  I assume the software may not know it needs to do this.  One option would be to configure the MDIO address for 0x1, but you may need to change the software so it knows the PHY attached to the respective MII port is configured to for a different MDIO address.

Regards,
Paul 

Hello Paul,

Thank you sooo much for that tip, the dp83848.c file from which I had copied the initialization part puts the PHY in Isolate mode initially but then I didn't take it out. Thanks a lot...it works fine now.

I do have a request for you, I've been having loads of trouble with my DDR initialization, I posted all my questions in the forum at..towards the end http://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/f/791/p/220673/793481.aspx#793481.

Could you please take a look when you get a chance and let me know how to fix this issue.

Thank you so much once again...

Santhosh