Is Spread Spectrum Clock Generator for AM335x supported?

All AM335x DPLL modules support spread spectrum clocking.

These are SSC registers described in the TRM.

CM_SSC_DELTAMSTEP_DPLL_*

CM_SSC_MODFREQDIV_DPLL_*

I have a medical device customer that is asking about the AM335x SSC support.  I’ve read through the TRM but do not have enough experience with SSC to understand what is being conveyed, or what the actual capabilities are just by looking at the register definitions.  It looks like MPU, DDR, DISP (LCD?), CORE, and PER domains are supported.

Does the PRCM generate SSC clocks for each domain, based on the SSC registers for each domain? 

Can the main clock be fed with an SSC source?

Am I missing anything in a typical EMI constrained use case?

Thank you!

The following section will be added to the TRM to describe SSC:

Spread Spectrum Clocking (SSC)
The module supports spread spectrum clocking (SSC) on its output clocks. SSC is used to spread the spectral peaking of the clock to reduce any electromagnetic interference (EMI) that may be caused due to the clock’s fundamental or any of its harmonics. When SSC is enabled the clock’s spectrum is spread by the amount of frequency spread, and the attenuation is given by the ratio of the frequency spread (Δf) and the modulation frequency (fm), i.e., [{10*log10(Df/fm)}-10] dB.
SSC is performed by changing the feedback divider (M) in a triangular pattern. Implying, the frequency of the output clock would vary in a triangular pattern. The frequency of this pattern would be modulation frequency (fm). The peak (ΔM) or the amplitude of the triangular pattern as a percent of M would be equal to the percent of the output frequency spread (Δf); that is, ΔM/M= Δf / fc.
Next mark with Finp the frequency of the clock signal at the input of the DPLL. Because it is divided to N+1 before entering the phase detector, so the internal reference frequency is Fref = Finp / (N + 1).
Assume the central frequency fc to be equal to the DPLL output frequency Fout, or fc= Fout = (Finp / (N + 1)) * (M / M2).
Since this is in band modulation for the DPLL, the modulation frequency is required to be within the DPLL's loop bandwidth (lowest BW of Fref / 70). A higher modulation frequency would result in lesser spreading in the output clock.
SSC can be enabled/disabled using bit CM_CLKMODE_DPLL_xxx.DPLL_SSC_EN (where xxx can be any one of the following DPLLs: MPU, DDR, DISP, CORE, PER). An acknowledge signal CM_CLKMODE_DPLL_xxx.DPLL SSC_ACK notifies the exact start and end of SSC. When SSC_EN is de-asserted, SSC is disabled only after completion of one full cycle of the triangular pattern given by the modulation frequency. This is done in order to maintain the average frequency.
Modulation frequency (fm) can be programmed as a ratio of Fref / 4; that is, the value that needs to be programmed ModFreqDivider = Fref / (4*fm). The ModFreqDivider is split into Mantissa and 2^Exponent (ModFreqDivider = ModFreqDividerMantissa * 2^ModFreqDividerExponent). The mantissa is controlled by 7-bit signal ModFreqDividerMantissa through CM_SSC_MODFREQDIV_DPLL_xxx.MODFREQDEV_MANTISSA bit field. The exponent is controlled by 3bit signal ModFreqDividerExponent through the CM_SSC_MODFREQDIV_DPLL_xxx.MODFREQDEV_EXPONENT bit field.

NOTE: Although the same value of ModFreqDivider can be obtained by different combinations of mantissa and exponent values, it is recommended to get the target ModFreqDivider by programming maximum mantissa and a minimum exponent.
To define the Frequency spread (Δf), ΔM must be controlled as explained previously. To define ΔM, the step size of M for each Fref during the triangular pattern must be programmed; that is,
ΔM = (2^ModFreqDividerExponent) * ModFreqDividerMantissa * DeltaMStep IF ModFreqDividerExponent <= 3ΔM = 8 * ModFreqDividerMantissa * DeltaMStep IF ModFreqDividerExponent > 3
DeltaMStep is split into integer part and fractional part. Integer part is controlled by 2-bit signal DeltaMStepInteger through the CM_SSC_DELTAMSTEP_DPLL_xxx.DELTAMSTEP_INTEGER bit field. Fractional part is controlled by 18-bit signal DeltaMStepFraction through the CM_SSC_DELTAMSTEP_DPLL_xxx.DELTAMSTEP_FRACTION bit field.
The frequency spread achieved has an overshoot of 20 percent or an inaccuracy of +20 percent.
If the CM_CLKMODE_DPLL.DPLL_SSC_DOWNSPREADis set to 1, the frequency spread on lower side is twice the programmed value. The frequency spread on higher side is 0 (except for the overshoot as described previously).

There is restriction of range of M values. The restriction is M-ΔM should be >= 20. Also, M+ΔM should be <= 2045. In case the downspread feature is enabled, M-2*ΔM should be >= 20 and M <= 2045.

Regards,

James

Please can you give me an example on how to activate the Spread Spectrum Clock in linux?

It is mentioned in AM335x_TRM that "SSC can be enabled/disabled using bit CM_CLKMODE_DPLL_xxx.DPLL_SSC_EN", but I have no clue how to do that on my  linux board.

Thanks.

G.

http://git.denx.de/?p=u-boot.git;a=blob;f=board/siemens/rut/board.c;h=f2b04768179533c2567212446e7057e4d0e03cfc;hb=c0dcece7d9925506a950e45028cbd25614aad791

DISPL_PLL_SPREAD_SPECTRUM

See attached source code. Use it in the board file of the linux kernel.

regards

Wolfgang

Hi guys

I'm trying to do spread spectrum on AM335x and I got this source code and tried to compile it. I am running TI Arago Kernel 3.12 from SDK7 and tried to compile it against that, but no matter what method I use I keep getting so many errors.

I tried to compile it as an independent source (used Linaro Cross GCC and G++) couldn't get it to work, as it failed with errors regarding definitions of "HZ" and "RCU":

In file included from ../include/linux/smp.h:12:0,

You have to configure and build the kernel before you can build a module against the kernel.

Look at your make output: it seems that the kernel tries to build a x86 module.

I already have built the kernel:

make -C . -j4 ARCH=arm CROSS_COMPILE=$CC zImage

Should I make modules too first?

I have a perfectly good zImage sitting in arch/arm/boot.

I made some progress today...However I'm still getting this error:

make -C ./ ARCH=arm CROSS_COMPILE=${CC}

maybe this info helps:
I tried putting the file and the makefile in:
1- 3.12/dither/
2- 3.12/arch/arm/mach-omap2/

Same result.
Is the Makefile correct?
What am I missing?

I made another change but still no success:

I moved the dither.c to arch/arm/mach-omap2/ and modified the Makefile there and added 

obj-m  += dither.o

and did make ARCH=.... modules but I keep getting the following errors:

I'm at a dead end...any help anyone?

The "implicit declaration" errors are because of missing include files. Remind that the sourcecode you get was meant to be included in the board file. The board file typically has include files to define ioremap, readl etc...
Just add the missing include files to your module sourcecode.

"‘make_spread_spectrum’ defined but not used " comes from the fact that you have missed to include a call to make_spread_spectrum() from the init function of your module.

You should read http://lwn.net/Kernel/LDD3/

regards
Wolfgang

Dear wolfgang,

Even I am trying to integrate the same in ti sdk 8 source code, Could you please let me know when & where ie., in which file (if it is in board file , am referring to am335x this board file: linux-3.14.26-g2489c02\arch\arm\mach-omap2\board-generic.c) could you please let me know where this make_spread_spectrum() function needs to be called in this file???

Kindly do the needful as early as possible,

Many Thanks in advance

I would like to provide some information on Spread Spectrum Clocking (SSC).

Additional timing margins are required when enabling Spread Spectrum Clocking (SSC). This prevents SSC from being enabled on any of the PLLs that source clocks to peripheral interfaces. We have determined SSC can be enabled on the MPU and Display PLL's since they only source clocks to dedicated circuits and interfaces that do not require low jitter clocks. The other PLLs will effect peripheral timing, so SSC should not be enabled on any PLLs other than MPU and Display.

You will need to configure the PLL to operate at a lower center frequency than maximum frequencies defined in the data sheet when SSC is enabled on the MPU and Display PLLs since SSC will spread the clock either side of the center frequency and the upper limit of the spread must not exceed the respective maximum frequency defined in the data sheet.

EMI is a system level design consideration and one of the things that can aggravate EMI is a non-optimized system design. If EMI is an issue, it may need to be resolved with proper PCB layout, PCB to PCB connector selection/signal-pin assignments, off-board connector selection and cable design. For example, signals propagating through connectors need to have a ground reference that does not create a large loop area for current to flow through such that it radiates like an antenna.

I cannot answer any questions related to implementing SSC in the various operating systems since I’m not a software support person. I just wanted to warn you that implementing SSC has some limitations and may not be easy to integrate with some of the complex power saving features currently implemented in the various operating systems.

Regards,
Paul