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About the Interrupt of GPIO

Yi Yin1
Intellectual 430 points

Hi

Reading the AM335x TRM, I see that there are two IRQ associated to GPIO0/1/2/3.

For a example of GPIO3: there are the related Registers:

GPIO_IRQSTATUS_RAW_0

GPIO_IRQSTATUS_RAW_1

GPIO_IRQSTATUS_0

GPIO_IRQSTATUS_1

GPIO_IRQSTATUS_SET_0

GPIO_IRQSTATUS_SET_1

・・・・

My question is that:

What is the difference  between the "XXX_0" and "XXX_1"?

Why are there two synchronous interrupt requests 1 and 2 ?

How can I proper use them?

For example,  when the GPIO3_7 Low Level is detected,

GPIO_IRQSTATUS_RAW_0 and GPIO_IRQSTATUS_RAW_1, which of the registers will be set?

Thanks!

  • 0
    TI__Guru**** 393215 points

    Please read section 25.3.3 in the AM335X TRM Rev. K. The two interrupt sets allow you to have two independent ISR's for each GPIO bank. It's up to you to decide which set - 0 or 1 you will use.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 430 points

    Hi Biser 

    Thanks for reply.

    I have read the Figure 25-3. Interrupt Request Generation. 

    But I still have a little doubt. 

    For example,  when the GPIO3_7 Low Level is detected,

    GPIO_IRQSTATUS_RAW_0 and GPIO_IRQSTATUS_RAW_1, which of the registers will be set?

    I think both of them will be set. Is it right?

    Thanks!

  • 0 in reply to Yi Yin1
    TI__Guru**** 393215 points

    When the host processor receives an interrupt request issued by the GPIO module, it can read the corresponding GPIO_IRQSTATUS_n register to find out which input GPIO has triggered the interrupt. After servicing the interrupt, the processor resets the status bit and releases the interrupt line by writing a 1 in the corresponding bit of the GPIO_IRQSTATUS_n register. If there is still a pending interrupt request to serve (all bits in the GPIO_IRQSTATUS_RAW_n register not masked by the GPIO_IRQSTATUS_SET_n, which are not cleared by setting the GPIO_IRQSTATUS_CLR_n), the interrupt line will be re-asserted.