Ethernet switch and gigabit phy connection to AM335x

Hi,

I will ask the factory team if this is possible.

Hi Biser, 

Is there any update on this issue from factory team.

Nothing so far. They should post directly here.

Yes, this is possible from a HW perspective. The AM335x switch downstream ports operate independently. Verify via the pinmux tool that there exists a valid pinmux configuration that allows for both RGMII and R/MII and any other interfaces required for your product.

I took a quick look at the switch you inquired about and have a couple of comments:

- I assume you will be using Mode 3 (of the switch) to allow a direct MAC-to-PHY connection from AM335x to the Micrel device's port 5 PHY.

- You will need to perform a timing analysis on the interface you choose (RMII/MII) for the switch to ensure that these devices can work together. The same will need to be done for the RGMII interface.

- Full access to the Micrel switch configuration registers are not available, even manually, via our MDIO interface as the Micrel uses a non-standard protocol. You will need to dedicate 2 GPIO's to bit-bang MDIO with this custom protocol.

Hi DK, 

Thanks for the confirmation, yes i have verified the  RGMII and R/MII pins with pinmux tool along with other interfaces. 

Now i have changed the ethernet switch with a Marvell device 88E6060. This is a six port switch. i want to expand to 5 ethernet ports for copper connection and interface with AM335x via RMII in PHY mode. 

Can you please confirm the compatibility with this switch. 

I am also planning to connect MDIO/MDC lines common for Ethernet Switch and Gigabit PHY, is this advisable?

I am new to these designs with microprocessor. Can you provide some insight to what timing analysis , i need to perform to check the the Ethernet Switch/ Gigabit PHY can work along with AM335x?

Ultimate suitability for a particular peripheral device, in this case the Marvell switch, is the responsibility of the customer as we can't claim expertise in another vendor's part. I have not seen the particular device used with ours, but a cursory review of their datasheet reveals nothing that jumps out at me as a problem. It does appear to support "R/MII PHY Mode" on more than one port which allows for the AM335x-supported MAC-to-PHY connection. Also, standard IEEE 802.3u clause 22 support for MDIO makes implementation much easier than having to bit-bang a custom interface. 

Connecting both "PHY"s to the same MDIO channel is fine. A single MDIO bus with multiple devices is the typical topology for this interface.

I thought I'd note that if  you plan on supporting Ethernet boot, that you must (practically) connect a PHY that supports a hardware-strap option for internal delay on both Rx and Tx channels.  I say practically because the other option is to introduce the required delays via ~10" of extra trace length on both clocks, which very often is not possible. If you don't plan on supporting Ethernet boot, this isn't an issue, but if you do...please refer to the AM335x Errata/Advisory 1.0.10 and search this forum for "internal delay" for more details. The issue is well documented here.

Whichever device you choose to connect to AM335x, you must perform a timing analysis to ensure that the devices on both sides of the interface are able to co-exist from an electrical timing (setup/hold/delay) perspective. As this is affected by trace length, I'd recommend verifying gross (ballpark) timing when choosing the PHY and then again when actually doing the layout.

On a more personal note, the publicly available datasheet for the Marvell switch is marked "Preliminary" and dated 2008. If this were my design, I'd be concerned about long-term availability of the part.