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AM3352 Non-muxed NOR boot

mamatha g
Intellectual 490 points
Other Parts Discussed in Thread: AM3352

Hi Biser,

I am  designing a system, where AM3352 is used as a system controller. The boot mode selected is Non-muxed NOR boot. I have selected a 1Gbit Non-mux parallel NOR flash from micron. This flash is used for booting as well as for data storage. The flash has 26 (A0-A25) address lines and 15 data lines. Kindly tell me How do I connect  this flash to AM3352 so that this device is mapped to 0x08000000 with CS0?

  • 0
    TI__Guru**** 393215 points

    Hi,

    Please read section 26.1.7.2 from the AM335X TRM Rev. K. Pay specific attention to subsection 26.1.7.2.2:

    "The pins that are not listed below are not configured by the ROM code and are left at power-on defaults. Specifically, external logic is needed to isolate the upper address lines (A12–A27) of the NOR flash from the device pins and drive them low during non-muxed NOR boot."

  • 0
    Intellectual 490 points
    Hello Biser,

    Thanks for the information, I went through the TRM. I have few more queries, kindly provide me the information.

    1. while booting does the ROM code, pin mux the GPMC_A0 to GPMC_A11 on mode 0 [ default mode is mode 7]. But in mode 0 GPMC_A26 and GPMC_A27 are muxed on GPMC_A0 and GPMC_A11 respectively.

    2. I need only GPMC_A0 to GPMC_A25 to address the flash, what should be driven on GPMC_A26 and GPMC_A27 so that the device is mapped to 0x08000000.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 490 points
    Hello Biser,

    Thanks for the information, I went through the TRM. I have few more queries, kindly provide me the information.

    1. while booting does the ROM code, pin mux the GPMC_A0 to GPMC_A11 on mode 0 [ default mode is mode 7]. But in mode 0 GPMC_A26 and GPMC_A27 are muxed on GPMC_A0 and GPMC_A11 respectively.

    2. I need only GPMC_A0 to GPMC_A25 to address the flash, what should be driven on GPMC_A26 and GPMC_A27 so that the device is mapped to 0x08000000.
  • 0 in reply to mamatha g
    TI__Guru**** 393215 points

    mamatha g said:
    1. while booting does the ROM code, pin mux the GPMC_A0 to GPMC_A11 on mode 0 [ default mode is mode 7]. But in mode 0 GPMC_A26 and GPMC_A27 are muxed on GPMC_A0 and GPMC_A11 respectively

    If this is a 16-bit device GPMC_A0 will not be driven (Table 7-5 from AM335X TRM). ROM code will initialize GPMC_A1 to GPMC_A11. ROM code will set Mode 0 to these address pins. All higher addresses of the NOR must be initially held low externally in order to boot from the device, because they will be left in their reset release state. Once code execution starts these higher addresses must be pinmuxed to GPMC mode early in the code (before code exceeds the 4k boundary).

    mamatha g said:
    2. I need only GPMC_A0 to GPMC_A25 to address the flash, what should be driven on GPMC_A26 and GPMC_A27 so that the device is mapped to 0x08000000.

    NOR address lines must be connected as given in Table 7-5, mapping is done internally.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 490 points
    Hello Biser,

    Thanks for your valuable information.
    The Micron flash which is selected for boot flash is a 16-bit device(density: 1Gbit) and has 16 bit data in each location (word addressing, it has A0 to A25 address lines only to address 128MB) hence I think we have to connect GPMC_A0 to flash_A0. Kindly suggest me how to interface this kind of memory to AM335x, which is not given in the datasheet.
  • 0 in reply to mamatha g
    TI__Guru**** 393215 points

    Please read Note 1 below TRM Table 7-5.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 490 points
    Thanks for your quick response,I am getting good calrity on the concept with your inputs. I have to meet tight deadlines and have to complete the schematic asap.

    If the ROM code initialize GPMC_A1 to GPMC_A11 and set Mode 0 to these address pins then how to access GPMC_A26 and GPMC_27 ,which are muxed on GPMC_A10 and GPMC_A11 in mode0.

    The Flash has following pins:
    A[25:0]
    D[15:0]
    CE#,OE#,WE#,CLK,ADV#,WP#,RST#,VPP,WAIT
  • 0 in reply to mamatha g
    TI__Guru**** 393215 points

    I finally understood your concern. What you should do is use 16-bit Address/Data Mux Mode. You will need to add a 16-bit address latch on the GPMC_AD[15:0] lines, that will be used to latch the lower address bits by nADV/ALE signal. You can use this schematic (http://processors.wiki.ti.com/images/9/9c/AM335X_GPEVM_DAUGHTERBOARD_3H0001_SCHEMATIC_REV1_2A.zip ) as a reference to get the idea. Look at page 3. Note that you will not need all the buffers used there. Instead of taking addresses from the LCD bus you will need to take them from the GPMC_AD bus and place a 16-bit latch instead of U2. This use case is TRM Table 7-5 fourth column.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 490 points
    Good Morning Biser,

    Yesterday meetings were scheduled for the whole day hence I was unable to reply back

    Once again thanks for your inputs.

    As suggest by you, I went through the schematic and read the Table 7-5.

    The flash memory( MT28GU01GAAA2EGC-0SIT ) selected for the project has
    interface option : x16 (Non-MUX) and x16 A/D MUX

    So I am thinking of using memory in x16 A/D MUX and then connect the processor and memory according to Figure 7-3 and follow third column of Table 7-5. Will this be fine.
  • 0 in reply to mamatha g
    TI__Guru**** 393215 points

    Yes, this should work without any external address latches. Just make sure you order the A/D mux option.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 490 points
    Biser,

    Can I use the unused adress line gpmc_a12 to gpmc_a27 as GPIO's
  • 0 in reply to mamatha g
    TI__Guru**** 393215 points

    Of course you can.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 490 points
    Hello Biser,

    Thanks for the advice. I have a doubt, kindly clarify

    In the TRM ,Figure 7-3. GPMC to 16 bit Adress/data-multiplexed memory , they have specified the connection between GPMC module,Device pins and the external memory. and in the booting section Table 26-10 Pins used for muxed NOR Boot is given. how to select the modes between XIP_MUX1 (with and without wait) or XIP_mux2 (with and without wait),On what parameters does it depend. Kindly clarify.
  • 0 in reply to mamatha g
    TI__Guru**** 393215 points

    Boot modes are selected by the SYSBOOT[15:0] pins. Table 26-7 from the TRM lists possible combinations.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 490 points
    Hello Biser,

    In the Table 26-10 defines pins used for muxed NOR BOOT.

    For eg : signal name : Wait1 ,Pin used in XIP_MUX1 is "none" and pin used in XIP_mux2 is "GPMC_CLK", Does this means that the gpmc signal "WAIT1" is provided on the pin "GPMC_CLK". If so , how do clock been suppleid in XIP_MUX2 mode.
  • 0 in reply to mamatha g
    TI__Guru**** 393215 points

    XIP boot is asynchronous only. Clock signal is not output, but GPMC_CLK pin is configured in XIP_MUX1 by ROM code. Otherwise you are correct, in XIP_MUX2 mode GPMC_WAIT1 signal is used, which is pinmuxed on GPMC_CLK pin.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 490 points
    Hello Biser,

    I have confusion in deciding XIP or XIP w/ WAIT mode.

    If XIP boot is asynchronous, then there is no need of WAIT signal know ( As per the memory datasheet " WAIT is deasserted during asynchronous reads).

    The selected memory for boot is parallel NOR Flash and has "VCC power valid to RST# deassertion = 300us(min)" and "96ns initial read access". Can I select XIP (without wait monitoring) because I want XIP_MUX1 ,SPI0 and UART0 boot combination.Kindly help me.
  • 0 in reply to mamatha g
    TI__Guru**** 393215 points

    With the read access time you shouldn't have any problem. About the reset time, if you use one of the recommended PMICs (TPS65910Ax or TPS65217x) and NOR reset pin is tied to AM335X warm reset there should be no problem too.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 360 points
    Hi,
    We also want to boot our AM3352 controller using NOR Flash of 1Gbit capacity in MUXED mode with 3.3V supply voltage.We have choosen S29GL01GS10DHI020 of Cypress manufacturer.
    A[0:25] lines -----> [0:15] muxed with data
    [16:25]sysboot lines in muxed mode
    DQ[0:15] lines
    CSn0 to CE#
    ADVn_ALE to D flip flop to provide latching
    OEn_REn to OE#
    WEn to WE#
    WPn to WP#
    But there is no provision for remaining signals (BE0n_CLE,BE1n and GPMC_Clk) in NOR Flash Memory.

    Can this pins be left unused ?
    Please provide some reference in this regard of booting using NOR flash with high memory capacity.

    Thanks in advance.