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Booting and programming the external FPGAs through AM3352 device

Other Parts Discussed in Thread: AM3352

Hi all,

We want to design a system using AM3352 600MHz uC where we want the Arm Processor to boot from an external OTP AT27C010. There after we want that the content of an external NOR Flash [consisting of bit files for two FPGAs and other operations of ARM] is checked and its Checksum is compared with the OTP. Then the bit files of both the FPGAs [Spartan 6 from Xilinx is our choice] be loaded with the bit files in the NOR Flash [Controlled by GPMC].

I want to ask the experts here that what shall be the best architecture for doing this entire activity. Can we even connect both the FPGAs, OTP and NOR Flash on single GPMC controller lines, if so what all are the things that need to be kept in mind.

Thanks and Regards..

Mohit

  • This seems to be a very old-fashioned way to boot such a system. You need 2 big storage devices (OTP and NOR Flash), and you have to program these devices.

    It is very easy to add a microSD connector to your target system, load every code and data onto a microSD device, and boot from microSD.

    And upgrading the system in the field is simple: just put new files onto the microSD.

    The layout of the system will be much simplier without OTP and NOR flash.

    regards

    Wolfgang

  • Dear Wolfgang,

    Thanks for the reply and sorry for delayed response as I was not in office.

    After working on beagle board and similar such boards, we have complete idea as to what you are telling and is appreciable but the requirement of the user is such that we have to do it in this manner.

    So I want to interface both the OTP[OTP AT27C010, consisting of initial boot code] and NOR Flash [S29GL_128S_01GS_00, parallel Spansion FLASH having configuration files for both the FPGAs and Processor Code] sharing the same GPMC bus. Is it possible?

    Further the same bus can it be used to program the spartan 6 FPGAs with the controller? I am slightly doubtful as to how the data from NOR FLASH is positioned time wise around OE\ control line of GPMC during read operation and whether they can be used as data and clock signal for SPARTAN 6 FPGA programming [SelectIMAP mode - parallel slave mode].

    Please help in this. Regards.
  • Interfacing OTP and NOR flash to the GPMC bus should be no problem. Use one chip select for OTP and one chip select for NOR.

    Interfacing the FPGA in parallel slave mode to the GPMC is not easy. There is an application note XAPP502 from xilinx, which is using an additional CPLD to interface the "GPMC" to the FPGA. The CPLD emulates a GPIO port.

    Instead of using a CPLD, you may opt to use a GPIO port of the CPU.

    I think it would be better to use Slave Serial Configuration. You may use a SPI from the CPU, so you can reach a high clock frequency. You should do a speed compare.

    regards

    Wolfgang

  • Dear Wolfgang,

    Based on your suggestion I have changed the programming mode in hardware for the two FPGAs as slave serial configuration with daisy chain.

    But Can you please provide me an application note where regarding update of the OMAP firmware in external NOR Flash. We know that the firmware will get updated and debugged using a USB to JTAG Converter. But hereafter which firmware utility running on OMAP processor will transfer the programming data to external NOR Flash is not clear to us. Again how can the FPGA bit stream files for daisy chain FPGAs be piggybacked along with this updated firmware is also not very clear to us.

    Requesting your help in it.

    Thanks and Regards.

     

  • Hi wolfgang,

    We wait for your reply on this if possible.

    Regards

  • Hi Mohit,

    sorry I can't help you with these tasks.

    regards

    Wolfgang