Additive Latency Value for DDR3 Memory

Takahiro Ogo said:

Does AM335x DDR Memory Controler configure AdditiveLatency of DDR3 MR1 when DDR Initilization is performed?

The AM335x memory controller always sets the MR1 additive latency field to a value of zero (disabled) during initialization.

Ogo-san,

Here is an explanation from our design team:

The read latency in DDR_PHY_CTRL_1 is for the DDR PHY. This should not be confused with the RL in the DDR device datasheet. Both of these are different.

Read latency of DDR PHY is used to transfer the read data from the DQS clock domain to its internal clock domain. The DDR PHY has a pseudo-synchronous FIFO that transfers read data from the DQS clock domain to its internal clock domain. The DDR PHY read latency defines how long the DDR PHY should wait before reading the FIFO using internal clock, after it has been written by the DQS clock during reads. The DDR PHY read latency number is defined by the round-trip latency of the system (IO delay + board delay + CL).

Therefore, changing DDR PHY read latency will not impact any waveforms observed on the DDR bus. It is strictly an internal timing for data transfer from DQS domain to DDR PHY clock domain.

Thanks for your great question!  I hope this helps clarify things.

Best regards,
Brad