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PWRSTCTRL/PWRSTST register of AM5728

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM5728

Hi,

I have some questions regarding some register of AM5728.

There are some register of powerdomain.

  PM_xxx_PWRSTCTRL[1:0]POWERSTATE bit 

  PM_xxx_PWRSTST[1:0]POWERSTATEST bit

Q1)

PM_xxx_PWRSTCTRL[1:0] bit = OFF

PM_xxx_PWRSTST[1:0] bit = Retention

If the above register are in this condition,  what situation is happened?

For example, if this is for DSP1,  DSP1 powerdomain is always OFF. And DSP logic/memory is retentioned. Is my understanding right?

Q2)

PM_xxx_PWRSTCTRL[1:0] bit = Retention

PM_xxx_PWRSTST[1:0] bit = Retention

If the above register are in this condition, what situation is happened?

Q3)

For reduced power consumption, PM_xxx_PWRSTCTRL[1:0] bit = OFF is recommended?

Please advise me .

Best regards,

Michi

 

  • 0
    TI__Guru**** 393215 points
    I will forward this to the AM57X team.
  • 0
    TI__Guru**** 161600 points

    Hi,

    Q1) & Q2):

    PM_xxx_PWRSTCTRL is a contorol register. I.e., when you set PM_DSP1_PWRSTCTRL[1:0]POWERSTATE = 0x0 you tell DSP1 to go to OFF state, in addition you can force the DSP1 to go to the pointed state, by setting: PM_DSP1_PWRSTCTRL[4]LOWPOWERSTATECHANGE = 0x1 => force change.

    Then wait until change is complete -> PM_DSP1_PWRSTCTRL[4]LOWPOWERSTATECHANGE = 0x0.

    And after that you can get the power state of DSP1, by reading the STATUS register PM_DSP1_PWRSTST[1:0]POWERSTATEST = 0x0.

    Have a look at Table 3-470. Forced Power Domain Low-Power State Transition.

    So your understanding is not correct. PM_xxx_PWRSTST[1:0] will give you the current state of the power domain. So when you set PM_xxx_PWRSTCTRL[1:0] bit = OFF -> power domain will transition to OFF, and once the transition is complete PM_xxx_PWRSTST[1:0] will ALSO read OFF.

    Michi Yama said:
    Q3)

    For reduced power consumption, PM_xxx_PWRSTCTRL[1:0] bit = OFF is recommended?

    Yes, OFF state is the lowest power state (lowest power consumption).

    Hope this helps.

    Best Regards,

    Yordan

  • 0 in reply to Yordan Kovachev
    Guru 10030 points
    Dear Yordan-san,

    Thank you for your quick reply.

    I have one more question regarding the power domain low power transition.

    As you know, there is "Table 3-457. Forced Power Domain Low-Power State Transition" in TRM.

    My customer tried to move the power domain to "retention" state by using these steps.
    But they can't do it. For power domain state transition, are there other registers setting needed?

    Please advise me again.

    I appreciate your quick reply.

    Best regards,
    Michi
  • 0 in reply to Michi Yama
    TI__Guru**** 161600 points
    Hi Michi,

    Which power domain is this? Have they considered Table 3-458. Not Supported Functionality(Registers and Bits) ?

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 10030 points

    Dear　Yordan-san,

    Thank you for your reply.

    I got an answer of my question from you on other thread (e2e.ti.com/.../1874785    ) .

    When I posted this question to E2E, I did not know the TRM had been updated, and the retention mode had been deleted from TRM.

    Please let me confirm one thing.  According to my understanding, PD_MPU is still supported " Retention" state, and not supported OFF state. Is it right?

    I appreciate your quick reply.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Guru**** 161600 points

    Hi,

    Michi Yama said:
    According to my understanding, PD_MPU is still supported " Retention" state, and not supported OFF state. Is it right?

    Yes, according to Section 3.7.5 PD_MPU Description in AM57xx TRM, your understanding is correct. 

    Best Regards, 

    Yordan