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AM5726 GPMC Output Clock

Akash Patel
Expert 6245 points
Other Parts Discussed in Thread: AM4376, AM5726

Hi team,

We are looking at the AM5726 and I see in the datasheet that the "Cycle time, output clock gpmc_clk period spec" (F0) is minimum 11.3 ns, which translates to about 88.5 MHz maximum. However with the AM4376, we are able to run this clock at 120 MHz.

  • Is the maximum frequency on the AM5726 actually only 88.5 MHz?
  • Why is this frequency lower than that of the AM4376?

Regards,

Akash Patel

  • 0
    TI__Guru**** 161600 points
    Hi Akash,

    Looping the design team to elaborate on this.

    Just FYI, as per AM437x device Data Manual the GPMC_FCLK should be 100MHz.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Expert 6245 points
    Hi team,

    Do we have any updates regarding this?

    Regards,
    Akash Patel
  • 0 in reply to Akash Patel
    TI__Mastermind 29290 points

    Hi Akash,

    88.67MHz is the fastest that GPMC on AM572x can operate, and the difference from AM437x is due to different input clocks and integer dividers.

    AM437x GPMC is capable of running GPMC_CLK at 100 MHz (OPP100) - not 120MHz, and derives this peripheral clock from the PD_PER_L3S_GCLK clock domain, which runs at 100MHz in OPP100. 100MHz is achievable with a divide by 1 clock divider.

    AM572x GPMC derives its clock from L3MAIN1_L3_GICLK, which is 266MHz. Divide by 2 (133MHz) is beyond the maximum frequency for timing closure, and the next step down (divide by 3) is 88.67MHz. This is the reason why AM572 GPMC operates at a slower max frequency than AM437x.

    Hope this helps,
    Mark

  • 0 in reply to Mark Mckeown
    TI__Expert 6245 points
    Hi Mark,

    Thanks for the detailed answer. Could you elaborate more on what you mean by "beyond the maximum frequency for timing closure?"

    Regards,
    Akash Patel
  • 0 in reply to Akash Patel
    TI__Guru 55425 points

    When you enable SSC, the PLL output frequency dithers up and down in frequency to spread the emissions across a wider frequency spectrum. Many peripherals must operate at specific frequencies for proper operation. So SSC is not support on peripheral clock domains.

    The DSS typically does not have this type of issue since many display devices support a wide range of operating frequencies. However, there may be a dependency on the attached display device.

    The MPU clock domain does not have this issue because it doesn't interface directly to any external devices.

    Internal circuits are designed to operate at the maximum frequency defined in the data sheet.  This frequency does not provide any additional margin for supporting the high frequency dithers that will be generated when SSC is enabled. Therefore, the center frequency of the PLL must be reduced enough to prevent the maximum frequency from the PLL from over-clocking the internal circuits when SSC is enabled.

    Regards,
    Paul

  • 0 in reply to Akash Patel
    TI__Mastermind 29290 points

    Hi Akash,

    STA timing closure on AM572x GPMC for an internal retiming path in sync supports up to ~89MHz, so operating beyond that frequency in sync mode is not recommended. This is reflected in the datasheet timing table - min clk period = 11.3ns (actually rounded up from 11.278ns / 88.667MHz = 266MHz / 3)

    Regards,
    Mark