PCM1863 with 27MHz clock PLL divider settings?

Found a solution, here are the settings for 27MHz to 48kHz, it works in this order:

i2cset  $ADC 0x0 0x0
i2cset  $ADC 0x25 0x7
i2cset  $ADC 0x26 0x3
i2cset  $ADC 0x27 0x3F
i2cset  $ADC 0x28 0x1
i2cset  $ADC 0x29 0x2
i2cset  $ADC 0x2a 0x0
i2cset  $ADC 0x2b 0xa
i2cset  $ADC 0x2c 0xfc
i2cset  $ADC 0x2d 0x0a

Wait here for a while, maybe for the PLL lock (P0.28 bit 4)?

Then do:

i2cset  $ADC 0x20 0x7e

Check the register and if the contents != 0x7e, set again.

Hi Lo,

I'm glad that you were able to find a solution. It seems you changed your calculation numbers, did you try without the wait before the last register write?

Justin

Hi Justin,

my 2nd post is a mix up from 44.1kHz and 48kHz, sorry. The settings in my fist post are correct for 48kHz.
I still got the issue that I have to wait for 'some time' before doing the last write to register 0x20.

I've got three PCM1863 on the board, so I'd like to set the clocking as fast as possible.
Could you please tell me if there's a bit I should poll before writing to register 0x20?

Regards,
Lo

Hi Lo,

I would suggest putting the part in digital standby (register 112) before making the PLL changes and then come out of digital standby after all the PLL changes have been made.

You stated that you have 48 KHz working, does that mean your settings for 44.1 KHz are still not working?

Justin

Hello Justin,

I use the following parameters for the PLL with an input clock of 27MHz and a L/R clock of 441.kHz / bit clock of 2.8224MHz:

# PLLCK = (PLLCKIN*R*K)/P = 98.304MHz

# values:

# P=3, R=1, K=10.352

# K splits up in J and D: J=10 D=352

I haven't found much on the PLL lock bit behaviour in the manual, so now I enable the digital stand-by (0x70 bit1) but that didn't do much. I have to set it at least twice using the sequence mentioned above.

Can you please post the recommended sequence to start the PLL?

The chapter 8.13.5 reads:

[please look it up in the manual as the rich text formatting currently does not work, it used to work a few days ago]

I assue the "/=" means "!=" so the second set of conditions applies.

Since 4 = J = 11 doesn't make sense, I assume that this too is a formatting mistake and the "=" signs must be replaced by "<" or "<=" signs. Since I use J=10, I'm safe either way.

Then there is the variable N that also enforces constraints:

[please look it up in the manual as the rich text formatting currently does not work, it used to work a few days ago]

N isn't described further in this chapter, but I guess this is the total divider ratio from the dividers in the grey box (page 29). Can you please confirm this?

Also in the grey box there is the unnamed divider which seems to be controlled by Page0 Reg 0x25, is that correct?

Setting those dividers to 1:64, 1:4 and 1:8 respectively that would result in a 1: 2048 divider which makes sense and the default settings match N in the example.

The register numbers mentioned below the example form the data sheet don't seem to match the register numbers from the register map. Please comment.

I've selected the ADC and the DSP 1/2 to source the clock form the PLL, which, when clocked with the settings above, would result in ~94MHz.

Should I modify the clock dividers for the ADC and the DSP1/2?


The most urgent is the PLL initialization sequence and the PLL lock check.


Best regards,

Lo

Hi Justin,

I use this sequence to set the PLL:

ADC=0x4b
i2cset -y 2 $ADC 0x0 0x0

i2cset -y 2 $ADC 0x25 0x7
i2cset -y 2 $ADC 0x26 0x3
i2cset -y 2 $ADC 0x27 0x3F

#clock selection
i2cset -y 2 $ADC 0x20 0x7e

#enable PLL
i2cset -y 2 $ADC 0x28 0x1

#set PLL, PLLCKIN is 27MHZ (video clock)
i2cset -y 2 $ADC 0x29 0x2
i2cset -y 2 $ADC 0x2a 0x0
i2cset -y 2 $ADC 0x2b 0xa
i2cset -y 2 $ADC 0x2c 0x60
i2cset -y 2 $ADC 0x2d 0x01


Can you please confirm that this sequence is permitted?



PS: rich text edit w/ images is still broken,.

Best regards,
Lo