Hi Team,
For PCM5102A, at what condition could it be into no output issue, while re-cycling VDD could make it work again ?
If VDD drop down to below 2.8V POR threshold, during normal working, and then recover gain, could PCM5102A work again ?
In D/S, it mention there is clock error detection principle, could you help share when this happens, how could it be normal again ?
I have customer evaluating this part, and meet output latch issue during input pulse power test, while the input I2S input are normal. Mute and then un-mute didn't help, and has to cycle VDD.
Thanks for your help.