TLV320AIC3254 - Noise Threshold

Hello Luis,

thank your for your response. Subsequent you find the register configuration that I use.

BCLK and WCLK are generated internally by the Audio-Codec. Due to the experience we made with this IC we now know that we need the clock signals for proper operation of the AGC function.

i spi8
# => SPI Kommunikation
# I2C Kommunikation
################################################################################################
# Software Reset
#######################################a########################################################
# select page 0
w 30 00 00
#
# Software Reset Reg. (Page 0 / Register 1, 0x01)
w 30 01 01
#
###############################################################################################

###############################################################################################
# SPI Interface Setting
###############################################################################################
w 30 00 00
# MISO Control, data output for SPI interface, I2C disabled
w 30 37 02
# SCLK Control, SPI clock
w 30 38 02

###############################################################################################
# Clock and OSR Settings
###############################################################################################
# select page 0
w 30 00 00
#
# Clock Setting Register 1 (Page 0 / Register 4, 0x04)
# Select PLL Clock Range -> Low PLL Clock Range (default)
# Select PLL Input Clock -> MCLK pin is input to PLL (default)
# Select CODEC_CLKIN -> MCLK pin is CODEC_CLKIN (default)
W 30 04 00
#
# Clock Setting Register 2 (Page 0 / Register 5, 0x05)
# PLL Power Up -> PLL is powered down (default)         => PLL is not used
# PLL divider P Value -> P = 1 (default)
# PLL divider R Value -> R = 1 (default)
W 30 05 11
#
# Clock Setting Register 3 (Page 0 / Register 6, 0x06)
# PLL divider J Value -> J = 4 (default)
w 30 06 04
#
# Clock Setting Register 4 (Page 0 / Register 7, 0x07)
# PLL divider D value (MSB) -> 0 (default)
# Clock Setting Register 5 (Page 0 / Register 8, 0x08)
# PLL divider D value (LSB) -> 0 (default)
w 30 07 00
w 30 08 00
#
# --- DAC Settings ---                                  => (not needed for AGC)
#
# Clock Setting Register 6, NDAC Values (Page 0 / Register 11, 0x0B)
# NDAC Clock divider Power Control -> powered up
# NDAC = 1 (default)
w 30 0B 81
#w 30 0B 82
#w 30 0B 01
#
# Clock Setting Register 7, MDAC Values (Page 0 / Register 12, 0x0C)
# MDAC Clock divider Power Control -> powered up
# MDAC = 2
w 30 0C 82
#w 30 0C 01
#
# DAC OSR Setting Register 1, MSB Value (Page 0 / Register 13, 0x0D)
# DAC OSR Setting Register 2, LSB Value (Page 0 / Register 14, 0x0E)
# DOSR = 128 (default)
w 30 0D 00
w 30 0E 80
#
# --- ADC Settings ---
#
# Clock Setting Register 8, NADC Values (Page 0 / Register 18, 0x12)
# NADC Clock Divider Power Control -> powered up
# NADC = 1
w 30 12 81
#
# Clock Setting Register 9, MADC Values (Page 0 / Register 19, 0x13)
# MADC Clock Divider Power Control -> powered up
# MADC = 2
w 30 13 82
#
# ADC OSR Setting Register (Page 0 / Register 20, 0x14)
# AOSR = 128 (default)
w 30 14 80
#
# --- General Purpose Clock (CDIV_CLK, CLKOUT)
#
# Clock Setting Register 10 ,Multiplexers (Page 0 / Register 25, 0x19)
# CDIV_CLKIN Clock Selection -> MCLK (default)
w 30 19 00
#
# Clock Setting Register 11, CLKOUT M divider value (Page 0 / Register 26, 0x1A)
# CLKOUT M divider power control -> powered down (default)
# CLKOUT M divider value -> 1 (default)
w 30 1A 01
#
# --- Audio Interface
#
# Audio Interface Setting Register 1 (Page 0 / Register 27, 0x1B)
# D7/6: 0/0 -> Interface Selection: I2S
# D5/4: 0/0 -> Data Word length: 16 bits
#   D3: 1   -> BCLK Direction: Output
#   D2: 1   -> WCLK Direction: Output
#   D1: 0   -> Reserved (default)
#   D0: 0   -> DOUT High Imp: no high impedance
w 30 1B 0C
#
# Audio Interface Setting Register 2 (Page 0 / Register 28, 0x1C)
# D7/0: 0x00 -> Data Offset Value: 0 BCLKs (default)
w 30 1C 00
#
# Audio Interface Setting Register 3 (Page 0 / Register 29, 0x1D)
# D7/6: 0/0 -> Reserved (default)
#   D5: 0   -> Loop Back Control: no Loopback
#   D4: 0   -> Loop Back Control: no Loopback
#   D3: 0   -> Bit Clock polarity: default polarity
#   D2: 1   -> Primary BCLK and WCLK Power Control: powered up, even when the codec is powered down
# D1/0: 1/1 -> BDIV_CLKIN Multiplexer Control: BDIV_CLKIN = ADC_MOD_CLK
w 30 1D 07
#
# Clock Setting Register 12,  BCLK N Divider (Page 0 / Register 30, 0x1E)
#   D7: 1   -> BCLK N Divider Power Control: powered up
# D6/0: 0   -> BCLK N Divider = 4
w 30 1E 84
#
# Audio Interface Setting Register 4, Secondary Audio Interface (Page 0 / Register 31, 0x1F)
# -> default
w 30 1F 00
#
# Audio Interface Setting Register 5 (Page 0 / Register 32, 0x20)
# -> default
# D7/4: 0000 -> Reserved (default)
#   D3: 0    -> Bit Clock Control: Primary Bit Clock is used
#   D2: 0    -> Word Clock Control: Primary Word Clock is used
#   D1: 0    -> ADC Word Clock Control: ADC WCLK is same as DAC WCLK
#   D0: 0    -> Data In Control: DIN is used
w 30 20 00
#
# Audio Interface Setting Register 6 (Page 0 / Register 33, 0x21)
#   D7: 0   -> BCLK Output Control: Generated Primary Bit Clock
#   D6: 0   -> Secondary BCLK Output Control: BCLK Input
# D5/4: 0/1 -> WCLK Output Control: Generated ADC_FS
# D3/2: 0/0 -> Secondary WCLK Output Control: WCLK input
#   D1: 0   -> Primary DOUT output control: Data Output from Serial interface
#   D0: 0   -> Secondary DOUT output control: DIN input (Loopback)
# w 30 21 00
w 30 21 10
#
###############################################################################################
###############################################################################################

################################################################################################
# Power Configuration
#######################################a########################################################
# select page 1
w 30 00 01
#
# Power Configuration Reg. (Page 1 / Register 1)
# Disable weak connection of AVDD with DVDD
w 30 01 08
#
# LDO Control Reg. (Page 1 / Register 2, 0x02)
# D7/6: DVDD LDO output is nominally 1.77V
# D5/4: AVDD LDO output is nominally 1,77V
# D3: Analog Block Power Control -> enabled
# D2: DVDD LDO Over Current Detect -> not detected (read only)
# D1: AVDD LDO Over Current Detect -> not detected (read only)
# D0: AVDD LDO Power Control -> Powered up
w 30 02 A1
#
# Common Mode Control Reg. (Page 1 / Register 10, 0x0A)
# Full Chip Common Mode is 0,75V
# Output CM for HPL and HPR is 1,25V
# Output CM for LOL and LOR is same as Full Chip CM
# Output of HPL and HPR is powered with LDOIN supply
# LDOIN input range = 1,8V...3,6V
w 30 0A 53
#
# Analog Input Quick Charging Config Reg. (Page 1 / Register 71, 0x47)
# Analog input power up time = 6.4ms
w 30 47 32
#
# Reference Power-up Config Reg. (Page 1 / Register 123, 0x7B)
# Force power up of reference with t=40ms
w 30 7B 05
#
###############################################################################################
# Input Routing
###############################################################################################
# Select page 1
w 30 00 01

# Right MICPGA Positive Terminal Input Routing Config Reg (Page 1 / Register 55, 0x37)
# 0x00 -> nothing is not routed to Right MICPGA
# 0x40 -> IN1R is routed to Right MICPGA with 10k resistance
# 0x80 -> IN1R is routed to Right MICPGA with 20k resistance
# 0xC0 -> IN1R is routed to Right MICPGA with 40k resistance
# 0x10 -> IN2R is routed to Right MICPGA with 10k resistance
# 0x20 -> IN2R is routed to Right MICPGA with 20k resistance
# 0x30 -> IN2R is routed to Right MICPGA with 40k resistance
# 0x04 -> IN3R is routed to Right MICPGA with 10k resistance
# 0x08 -> IN3R is routed to Right MICPGA with 20k resistance
# 0x0C -> IN3R is routed to Right MICPGA with 40k resistance
w 30 37 40

# Right MICPGA Negative Terminal Input Routing Config Reg (Page 1 / Register 57, 0x39)
# 0x00 -> nothing is routed to Right MICPGA
# 0x10 -> IN1L is routed to Right MICPGA with 10k resistance
# 0x20 -> IN1L is routed to Right MICPGA with 20k resistance
# 0x40 -> CM is routed to Right MICPGA via CM1R with 10k resistance
# 0x80 -> CM is routed to Right MICPGA via CM1R with 20k resistance
w 30 39 10

###############################################################################################
###############################################################################################
# ADC Setup
###############################################################################################
# Select page 0
w 30 00 00

# ADC Channel Setup Register (Page 0 / Register 81, 0x51)
# Left Channel ADC Power Control -> powered up
# Right Channel ADC Power Control -> powered up
# ADC Volume Control Soft-Stepping Control -> 1 gain step per ADC Word Clock
w 30 51 C0
#
# ADC Fine Gain Adjust Register (Page 0 / Register 82, 0x52)
# Left ADC Channel Mute Control -> un-muted
# Right ADC Channel Mute Control -> un-muted
w 30 52 00
#
# Left ADC Channel Volume Control (Page 0 / Register 83, 0x53)
# -> 0dB
w 30 53 00
#
# Right ADC Channel Volume Control (Page 0 / Register 84, 0x54)
# -> 0dB
w 30 54 00
#
# Select page 1
w 30 00 01
#
# ADC Power Tune Configuration (Page 1 / Register 61, 0x3D)
# -> PTM_R4 = high performance
w 30 3D 00
#
###############################################################################################
# AGC Setup
###############################################################################################
# Select page 0
w 30 00 00

# Right Channel AGC Control Register 1 (Page 0, Register 94, 0x5E)
# (0dBFS: 550mV @ Vref = 0,75V)
# 0xA0 -> Right Channel AGC enabled
#         Right Channel Target Level -> -10.0dBFS
#         Right Channel AGC Gain Hysteresis Control -> disabled
# 0xE0 -> Right Channel AGC enabled
#         Right Channel Target Level -> -20.0dBFS
#         Right Channel AGC Gain Hysteresis Control -> disabled
# 0xF0 -> Right Channel AGC enabled
#         Right Channel Target Level -> -24.0dBFS
#         Right Channel AGC Gain Hysteresis Control -> disabled
w 30 5E f0
#
# Right Channel AGC Control Register 2 (Page 0, Register 95, 0x5F)
# Right Channel AGC Hysteresis Setting -> 1.0dB
# Right Channel AGC Noise Threshold -> disabled
w 30 5F 00
#
# Right Channel AGC Control Register 3 (Page 0, Register 96, 0x60)
# 0x50 -> Right Channel AGC Maximum Gain Setting -> 40dB (Faktor 100)
# 0x57 -> Right Channel AGC Maximum Gain Setting -> 43,5dB (Faktor 150)
w 30 60 0C
#
# Right Channel AGC Control Register 4 (Page 0 / Register 97, 0x61)
# Right Channel AGC Attack Time -> 1 * 32 ADC Word Clocks (default)
# Right Channel AGC Attack Time Scale Factor Setting -> 1 (default)
w 30 61 00
#
# Right Channel AGC Control Register 5 (Page 0 / Register 98, 0x62)
# Right Channel AGC Decay Time Setting -> 1 * 512 ADC Word Clocks (default)
# Right Channel AGC Decay Time Scale Factor Setting -> 1 (default)
w 30 62 00
#
# Right Channel AGC Control Register 6 (Page 0 / Register 99, 0x63)
# Right Channel AGC Noise Debounce Time Setting -> 0 (default ?)
w 30 63 00
#
# Right Channel AGC Control Register 7 (Page 0 / Register 100, 0x64)
# Right Channel AGC Signal Debounce Time Setting -> 0 (default ?)
w 30 64 00
#
###############################################################################################
###############################################################################################

###############################################################################################
# Output Routing
###############################################################################################
# Select page 1
w 30 00 01
#
# HPL Routing Reg. (Page 1 / Register 12)
# 0x04 -> IN1L is routed to HPL
# 0x02 -> MAL is routed to HPL
# 0x01 -> MAR is routed to HPL
w 30 0C 01
#
# HPR Routing Reg. (Page 1 / Register 13)
# 0x04 -> IN1R is routed to HPR
# 0x02 -> MAR is routed to HPR
# 0x01 -> HPL is routed to HPR (use when HPL and HPR is output is powered by AVDD)
w 30 0D 02
#
###############################################################################################
# Output Settings
###############################################################################################
# Select page 1
w 30 00 01
#
# Output Driver Power Control Reg. (Page 1 / Register 9)
# HPL is powered up, HPR is powered up
# MAL is powered up, MAR is powered up
w 30 09 33
#
###############################################################################################
# Gain Settings
###############################################################################################
# Select page 1
w 30 00 01
#
# IN1L to HPL Volume Control Reg. (Page 1 / Register 22)
# 0x75 -> Mute, 0x00 -> 0dB .. 0x74 -> -72.3dB
# 0x14 -> -10dB, 0x10 -> -8dB, 0x0C -> -6dB, 0x28 -> -20,1dB 0x50 -> -40,2dB
w 30 16 00
#
# Right MICPGA Volume Control Reg. (Page 1 / Register 60, 0x3C)
# 0x00 -> 0dB, 0x0C -> 6dB, 0x14 -> 10dB, 0x3f -> 31,5dB
w 30 3C 3f
#
# Mixer Amplifier Right Volume Control Reg. (Page 1 / Register 25, 0x19)
# 0x00 -> 0dB, 0x0C -> -5.8dB, 0x15 -> -10.1dB
# 0x0A -> -4.8dB
# 0x12 -> -8.5dB
# 0x21 -> -18.1dB
w 30 19 0a
#
# HPL Driver Gain Setting Reg. (Page 1 / Register 16)
# HPL is not muted, driver gain is 0dB
w 30 10 00
#
# HPR Driver Gain Setting Reg. (Page 1 / Register 17)
# HPR is not muted, driver gain is 0dB
w 30 11 00
#

Hi, Markus,

Just to confirm, are you using the MAL/MAR connections from the PGA to the HP outputs?

The MAL/MAR lines cannot be used with the AGC function. If you're looking to route the PGA to the HP outputs, I would suggest to use a digital loopback. This function routes the ADC output to the DAC input. So, all the functionalities such the AGC will be applied to the data.

Please let me know if you have questions or comments.

Best regards,
Luis Fernando Rodríguez S.

Hello Luis,
yes I use the MAR connection from the PGA to the HP output.
The AGC feature is available in this path. Just the noise threshold feature does not work.

Meanwhile I observed the I2S-Interface to check the behavior. The I2S-output shows the correct behaviour w.r.t. the noise threshold. It does not matter if MAR is powered up or powered down.

I do now have a question regarding 0dBFS. At which input voltage level will the ADC output 0dBFS? Using an I2S analyzer the maximum output level that I can measure is -12dBFS, then the signal is clipped.

Best regards
Markus

Hi, Markus,

The full-scale voltage (0 dB) is marked in the datasheet as 0.5Vrms. You should obtain the ADC output 0dBFS if AVDD = 3.3V. If AVDD = 1.5V, the full-scale output voltage will be fixed at 0.375Vrms.

Please let me know if you have more questions or comments.

Best regards,
Luis Fernando Rodríguez S.

Hello Luis,

unfortunately, I dont understand that. Using a figure that we received earlier, I tried to visualize the issue:

Questions:

1.) Is the figure applicable for the TLV320AIC3254?

2.) Are the following assumptions correct: 0dBFS at (AVDD / 2) / SQRT(2) ?

3.) For an input signal with an amplitude of 0,375Vrms the maximum output in digital domain woud be -3dBFS (see calculation in figure). Is this correct?

4.) If the stated points are correct, why does the ADC output signal clip at -12dBFS?

Best regards,

Markus

Hi, Markus,

Effectively, the figure that you shared is applicable for the TLV320AIC3254. I will try to explain how it works.

The TLV320AIC3254 has two possible common-mode voltages for the analog inputs: CM = 0.75V and CM = 0.9V. This means that the input voltage will be placed on this reference. For example, if a sine wave signal is applied at the input, the mean voltage would be 0.9V or 0.75V (depending of the configuration). So, as your figure explains, AVDD is the max value (0x7FFF at 16-bits). The max input voltage would be AVDD - 0.75V or AVDD - 0.9V. This would create a clipping effect.

We actually suggest 0.375Vrms or 0.5Vrms because the PGA has less gain error for these typical values (-0.05 dB). A lower or higher voltage would increase the gain error. However, the clipping effect is reached if 0V or AVDD is applied at the ADC.

I hope to have been clear. Please let me know if you have more questions or comments.

Best regards,
Luis Fernando Rodríguez S.

Hello Luis,

thank you for your feedback.

Since you always responded quickly, we were able to clarify the subject together. I appreciate that.

Best regards.

Markus