Interfacing ADS54RF63 EVM and DAC34SH84 EVM with Xilinx Virtex 6 ML605

Hi,

Take a look at the Application Note http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slaa545&fileType=pdf where we have an ADC EVM connected to an FPGA development platform as well as a DAC EVM to the same platform, doing a pass through of the data from the ADC to the DAC.  Granted, this is a different vendor of FPGA than you are using, and different data converter EVMs - but you should get the idea.  We do not have example code for every combination of data converter and FPGA vendor.  That would not be possible.   You would have to develop your own FPGA code, perhaps with support from your FPGA vendor, using the principles illustrated in things like this app note i pointed out.

For meeting timing from your ADS54RF63 EVM into your FPGA, please note that the datasheet for the ADS54RF63 shows a timing relationship that is commonly called source-synchronous or source-aligned.  This means that the 'clock' edge transitions at the same time as the data bit transitions - meaning you have no setup and hold time for the data around the clock signal.  The clock signal (called the DRY signal from the ADS54RD63) has to be delayed in the FPGA by some amount in order to make the timing into the FPGA be met properly.  The Xilinx conveniently gives you a function on every LVDS input called an Idelay, where you can delay the signal by some set amount of time.  We used that to meet timing into a Virtex4 on our TSW1200.  Please see the attched sketch of how this IDELAY can be used.  You would have to use the STA (Static Timing Analysis) tools from your Xilinx toolset to determine what tap settings would be needed in YOUR design to meet timing into the Virtex6.  It will not be the same as into a Virtex4.   If you are not familar with the tool set for your FPGA, you would need support from your FPGA vendor on how to meet timing.  But the attaced sketch is howI would recommend implementing it.

Regards,

Richard P.

Hi Richard,

 Thanks a lot for the quick reply. I had gone through the application note you had sent. I shall look into it once again, and try to note the principles illustrated therein. 

 In the meantime, it would also be great if you could provide me with vhdl code for the TSW1200, so that it would help me get a better idea of the principles implemented. With respect to the design you had posted, I understand that IDELAY could be put up in the clock lines so as to account for the delays introduced by the device lines ( Am I right?). But, why should the data lines too need the IDELAY?

Thanking You,

Basil M.

Hi Richard,

 I went on to interface the ADS54RF63EVM board and DAC34SH84EVM board with a Xilinx Virtex 6 ML605 board.

1. I am using the 19.2 MHz crystal source inside the DAC34SH84 to generate a 270 MHz clock for both the DAC board, and FPGA board. I am using this clock inside the FPGA to send to the ADC board, to use at it's clock. 
 -- Is there any problem with this ?

2. I am using a 3 Mhz, 1 V p-p sine wave to send to the ADS54RF63EVM board, and I expect a sine wave output at the oscilloscope at the DAC output. 
 -- But, what I observe is a waveform (non-sinusoidal, 22 MHz, 2.2 Vp-p)  which does NOT change with any change in the input frequency !
 -- This waveform remains even after I switch of the ADC input. Could you give me any help in suggesting why this could happen?
 -- Once I remove the ADC clock (which is coming from FPGA), the waveform is not there. Does this mean that there is some sort of clock leakage ?


Thanks a lot in advance,
Basil

Hi,

Answered in response to your posting at http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/p/335920/1172651.aspx#1172651

Please dont post multiple copies of the same question , thanks.

Regards,

Richard P.