Interfacing of virtex-6 FPGA board with DAC34SH84 and ADS54RF63

Pramod Kumar2

Other Parts Discussed in Thread: CDCE62005, DAC34SH84

Hello!

Even though there are posts related to this topic and read them, not able to figure out what is the problem is my setup.

What I have been doing is as follows

1. Giving a input signal of 2 MHz and a clock of 48MHZ to ADC.

2. The digital data coming out of ADC is being written if a FIFO (which I have defined in FPGA) with write clock of 96 MHz which is the output of MMCM block(1) in FPGA, and the input to this MMCM block(1) is coming from ADC itself (Same clock of 48 MHz that is provided to ADC as clock).

3. Reading the FIFO with a clock of 96 MHz which is the output of another MMCM block(2) in FPGA and input to this MMCM block(2) is coming from the DAC board.

4. The output of MMCM block(2) is also being used for DATA_CLK for DAC.

In short there are two MMCM block in my design and and I am feeding them from different clocks.One clock is coming through ADC (generated from High frequency function generator) and other is coming through DAC which is generated by CDCE62005.

And I am using FMC connectors to connect ADC and DAC to FPGA board.

Problem is: I am not getting any signal at the output of DAC, which is expected to be 2 MHz signal that I feed to ADC. I wanted to attach the DAC configuration file as well as VHDL code. but there is no link where i can do so.

Please help!

Regards

Pramod singh

over 9 years ago

0 Ebenezer Dwobeng over 9 years ago

TI__Genius 9695 points

Hi Pramod,

It will be good to independently confirm that the DAC to FPGA interface works before piping data from the ADC to the DAC. I will also suggest that you follow the recommendations in the thread below to confirm that the DAC34SH84 works.

http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/359131.aspx

Thanks,

Eben.

0 Pramod Kumar2 over 9 years ago in reply to Ebenezer Dwobeng

Prodigy 70 points

Hello Ebenezer!!

Thanks a lot for your quick reply. Your suggestion worked quit well, I went through the link you have provided and it was ver y useful. It seems DAC is got configured well now. I got some output but not exactly that I am expecting. The signal I am getting is quit noisy and distorted. Bellow is the waveforms that i am getting.

The yellow one is the output that I am getting out of DAC, and green one is the input that I am feeding to ADC.

I am totally blank why this output is like this even though I have considered setup and hold time as well. Can you please suggest me what changes i can make to get expected waveform. I am attaching VHDL code .ucf file and DAC configuration GUI file here that I am using.Please help.

1205.mine_1119_260M_locked.txt

   x00	   x009C
   x01	   x100E
   x02	   x0000
   x03	   xF000
   x04	   xBFFF
   x05	   xB860
   x06	   x2800
   x07	   xFFFF
   x08	   x0000
   x09	   x8000
   x0A	   x0000
   x0B	   x0000
   x0C	   x0400
   x0D	   x0400
   x0E	   x0400
   x0F	   x0400
   x10	   x0000
   x11	   x0000
   x12	   x0000
   x13	   x0000
   x14	   x0000
   x15	   x0000
   x16	   x0000
   x17	   x0000
   x18	   x20F7
   x19	   x2074
   x1A	   xAC20
   x1B	   x0800
   x1C	   x0000
   x1D	   x0000
   x1E	   x1111
   x1F	   x1144
   x20	   x1101
   x22	   x1B1B
   x23	   xFFFF
   x24	   x0000
   x25	   x7A7A
   x26	   xB6B6
   x27	   xEAEA
   x28	   x4545
   x29	   x1A1A
   x2A	   x1616
   x2B	   xAAAA
   x2C	   x0000
   x2D	   x0004
   x2E	   x0000
   x2F	   x0000
   x30	   x0000
   x7F	   x0000
CDCE62005 Registers
Freq:0.000000MHz
Address	Data
00		00400000
01		81840321
02		80120302
03		C1840303
04		C13C0304
05		000C1A85
06		84BF2AF6
07		151877F7
08		20001808

0525.vhdl.txt

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_signed.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;

entity adc_to_fifo is
port(

	-- inputs from the ADC --
		-- Data
	adc_inp			: in std_logic_vector (11 downto 0);
	adc_inn			: in std_logic_vector (11 downto 0);
	
		-- Data Ready (Clock from ADC)
	dry_clk_inp			: in std_logic;
	dry_clk_inn			: in std_logic;
	
		-- Ref 200MHz clock
	SYSCLK_P		: in std_logic;
	SYSCLK_N		: in std_logic;
	
	
		-- FPGA clock from DAC
		-- FPGA clock from DAC
   fpga_clk_inp	: in std_logic;
	fpga_clk_inn	: in std_logic;
	
	-- 2.11 starts
	PARITYP			: out std_logic;						--PARITYABP: Sync the FIFO pointer or act as a parity input for the AB-data bus
	PARITYN			: out std_logic;
	SYNCP		    : out std_logic;	--SYNCP: allow complete reversal of the data interface when setting the rev_interface bit in register config.
	SYNCN			: out std_logic;
	FIFO_ISTRP		: out std_logic;						--ISTRP: act with SYNC, PARITY.
	FIFO_ISTRN		: out std_logic;
	
		-- Data clock to DAC
	DATA_CLKP		: out std_logic;						--DATACLKP: LVDS positive input data clock. Data are lutched on both edges of DATACLKP/N.
	DATA_CLKN		: out std_logic;
	
		-- SMA out for clock to ADC
	sma_outp			: out std_logic;
	sma_outn			: out std_logic;
	
	-- output to DAC
	IO_DAP			: out std_logic_vector (15 downto 0);		
	IO_DAN			: out std_logic_vector (15 downto 0);
	-- 2.11 ends
	
-- #2.8 	led_1, led_2			: out std_logic; removing led_1, led_2 from output
	led_out        : out std_logic_vector (7 downto 0);		-- for counter
	rst            : in std_logic
	
--	fifo_rst_in : IN std_logic;
--	wr_en_in, rd_en_in : in std_logic; #2.10
			
-- 2.11	fifo_out	: out std_logic_vector (11 downto 0) 
	
);
end adc_to_fifo;

architecture Behavioral of adc_to_fifo is

-- ----------------------------- Constants ---------------------------

	constant Low  			: std_logic	:= '0';
	constant High 			: std_logic	:= '1';
	constant LowWord		: std_logic_vector (4 downto 0) := "00000";

-- --------------------------------------------Component Declaration ------------------------------------------------------------------------
	
	
	COMPONENT counter1 is
	port(
		CLK1_counter : in std_logic;
		LED_counter : out std_logic_vector(7 downto 0);
		RESET : in std_logic
		);
	END COMPONENT;



COMPONENT fifo_generator_v9_3
 PORT (
    rst : IN STD_LOGIC;
    wr_clk : IN STD_LOGIC;
    rd_clk : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
    wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
    full : OUT STD_LOGIC;
    wr_ack : OUT STD_LOGIC;
    overflow : OUT STD_LOGIC;
    empty : OUT STD_LOGIC;
    valid : OUT STD_LOGIC;
    underflow : OUT STD_LOGIC
  );
END COMPONENT;
	-- ------------------------------------------------Signal declaration---------------------------------------

	-- #2.8 
	--Debug Nets
	-- signal ovr_in_s : std_logic;
	signal debug_signal1	: std_logic_vector(11 downto 0);
	signal led_1, led_2 : std_logic;
	signal dry_clk_s, dry_clk_2x 		: std_logic;
	signal clkout4pin, CLKFBOUTpin, CLKFBOUTBpin, CLKFBINpin: std_logic;
	signal clkout4pin_1, CLKFBOUTpin_1, CLKFBOUTBpin_1, CLKFBINpin_1: std_logic;
	signal data_clk, data_clk1, pwrdwn	: std_logic;
	signal sync, fifo_istr, parity		: std_logic;
	signal    countER     				: integer range 0 to 1:=0;
	
--	signal	fpga_in						: std_logic_vector (11 downto 0) := (others=>'0');

	signal	IO_DA						: std_logic_vector (15 downto 0) := (others=>'0');
	
	-- checking
	--signal 	led_out_1,led_out_2			: std_logic_vector (7 downto 0);
	
	signal ref_200_clk_s, ref_clk200_bufg	: std_logic;
	signal dry_clk_delayed_s, dry_clk_bufio_s, dry_clk_bufr_s,dry_clk_bufg_s	: std_logic;
	signal adc_data_s, data_delayed_s, fifo_out	:std_logic_vector (11 downto 0) := (others=>'0');
	signal	rst_adc, Ready_idelay_out	: std_logic;
	signal ff_data : std_logic_vector (11 downto 0);
	signal full, wr_ack, empty, overflow, valid, underflow : std_logic;
	signal fpga_clk_s	: std_logic;
	
	-- 2.10 
	signal fifo_rst, wr_en_in, rd_en_in : std_logic;
	
	signal led_out2, led_out3 : std_logic_vector (7 downto 0); -- 2.11
	
	signal clkout0pin, chip_780_clk : std_logic;--2.14
	
begin

	IBUFGDS_inst_refclk1 : IBUFGDS
	generic map (
	DIFF_TERM => FALSE, -- Differential Termination
	IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards
	IOSTANDARD => "DEFAULT")
	port map (
		O => ref_200_clk_s, -- Clock buffer output
		I => SYSCLK_P, -- Diff_p clock buffer input (connect directly to top-level port)
		IB => SYSCLK_N -- Diff_n clock buffer input (connect directly to top-level port)
	);

	-------------- BUFG for ref_200M ---------------------
	BUFG_clk200inst : BUFG
	port map (
		O => ref_clk200_bufg, -- 1-bit Clock buffer output
		I => ref_200_clk_s -- 1-bit Clock buffer input
	);
	
	
	--2. DRY path
	
	-- -----------buffer for DRY--------
	IBUFGDS_inst_clk1 : IBUFGDS
	generic map (
	DIFF_TERM => FALSE, -- Differential Termination
	IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards
	IOSTANDARD => "DEFAULT")
	port map (
		O => dry_clk_s, -- Clock buffer output
		I => dry_clk_inp, -- Diff_p clock buffer input (connect directly to top-level port)
		IB => dry_clk_inn -- Diff_n clock buffer input (connect directly to top-level port)
	);
	
	
	
	--	-------------IODELAY for DRY------------------
	
	-- This IDELAY has : input  = dry_clk_s , output = dry_clk_delayed_s, clock = clk_for_delay, inc, rst, en = need to find out
	
	
   IODELAYE1_inst_clk1 : IODELAYE1
	generic map (
      CINVCTRL_SEL => FALSE,         -- Enable dynamic clock inversion ("TRUE"/"FALSE") 
      DELAY_SRC => "I",                -- Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
      HIGH_PERFORMANCE_MODE => TRUE, -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
      IDELAY_TYPE => "FIXED",        -- "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE" 
      IDELAY_VALUE => 20,               -- Input delay tap setting (0-32)
-- v2.13 made idelay value =2 
      ODELAY_TYPE => "FIXED",          -- "FIXED", "VARIABLE", or "VAR_LOADABLE" 
      ODELAY_VALUE => 0,               -- Output delay tap setting (0-32)
      REFCLK_FREQUENCY => 200.0,       -- IDELAYCTRL clock input frequency in MHz
      SIGNAL_PATTERN => "DATA"         -- "DATA" or "CLOCK" input signal
   )
   
			
   port map (
      CNTVALUEOUT => open , -- 5-bit output - Counter value for monitoring purpose
      DATAOUT => dry_clk_delayed_s,       -- 1-bit output - Delayed data output
      C => Low,                     -- 1-bit input - Clock input
      CE => Low,                   -- 1-bit input - Active high enable increment/decrement function
      CINVCTRL => Low,       -- 1-bit input - Dynamically inverts the Clock (C) polarity
      CLKIN => Low,             -- 1-bit input - Clock Access into the IODELAY
      CNTVALUEIN => LowWord,   -- 5-bit input - Counter value for loadable counter application
      DATAIN => Low,	          -- 1-bit input - Internal delay data
      IDATAIN => dry_clk_s ,      -- 1-bit input - Delay data input
      INC => Low,                 -- 1-bit input - Increment / Decrement tap delay
      ODATAIN => Low,         -- 1-bit input - Data input for the output datapath from the device
      RST => rst, -- 10.1                 -- 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
                                  -- ODELAY_VALUE tap. If no value is specified, the default is 0.
      T => High                      -- 1-bit input - 3-state input control. Tie high for input-only or internal delay or
                                  -- tie low for output only.

   );
	

	
	MMCM_BASE_inst_1 : MMCM_BASE
	generic map (
	BANDWIDTH => "OPTIMIZED", -- Jitter programming ("HIGH","LOW","OPTIMIZED")
	
	CLKFBOUT_MULT_F => 16.0, -- v3.1 v4.1
	CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (0.00-360.00).

	CLKIN1_PERIOD => 20.833, -- v3.1   48kHz)		-- v4.1
	CLKOUT0_DIVIDE_F => 1.0, -- Divide amount for CLKOUT0 (1.000-128.000).
	
	CLKOUT4_DUTY_CYCLE => 0.5,
	
	CLKOUT4_PHASE => 0.0,
	
	CLKOUT4_DIVIDE => 8, --v3.1
	CLKOUT4_CASCADE => FALSE, -- Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
	CLOCK_HOLD => FALSE, -- Hold VCO Frequency (TRUE/FALSE)

	DIVCLK_DIVIDE => 1, -- Master division value (1-80) -- v4.1
					-- 5 so that 250 Mhz * (5/5) = 250 Mhz Version 1.2
	REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
	STARTUP_WAIT => FALSE -- Not supported. Must be set to FALSE.
	)

	port map (
	
	CLKOUT4 => clkout4pin_1, -- 1-bit output: CLKOUT0 output
	
	CLKFBOUT => CLKFBOUTpin_1, -- 1-bit output: Feedback clock output
	CLKFBOUTB => CLKFBOUTBpin_1, -- 1-bit output: Inverted CLKFBOUT output
	
	LOCKED => Led_1, -- 1-bit output: LOCK output
	
	CLKIN1 => dry_clk_delayed_s, -- 2.13
	
	PWRDWN => PWRDWN, -- 1-bit input: Power-down input
	RST =>  RST, -- 1-bit input: Reset input
	-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
	CLKFBIN => CLKFBINpin_1 -- 1-bit input: Feedback clock input
	);
	
	-- ----------Bufg for fback ---------------------
	-- version 1.1
	BUFG_inst_1 : BUFG
	port map (
	O => clkfbinpin_1, -- 1-bit output: Clock buffer output
	I => clkfboutpin_1 -- 1-bit input: Clock buffer input
	);


-- ------- bufg for dry_clk_2x ------------------
	-- version 1.1
	BUFG_inst11 : BUFG
	port map (
	O => dry_clk_2x, -- 1-bit output: Clock buffer output
	I => clkout4pin_1 -- 1-bit input: Clock buffer input
	);
			
		
	
	
	-- 3. ADC inputs
	
	---------- ADC data input to FPGA -------------------
	ADC_IN_GEN: for j in 0 to 11 generate
	begin

	IBUFDS_inst_IO_DA : IBUFDS
	generic map (
		DIFF_TERM => FALSE, -- Differential Termination
		IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards
		IOSTANDARD => "DEFAULT")
		port map (
			O => adc_data_s(j),
			I => adc_inp(j),
			IB => adc_inn(j)
		);
		
	IODELAYE1_inst : IODELAYE1
	generic map (
		CINVCTRL_SEL => FALSE,         -- Enable dynamic clock inversion ("TRUE"/"FALSE") 
		DELAY_SRC => "I",                -- Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
		HIGH_PERFORMANCE_MODE => TRUE, -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
		IDELAY_TYPE => "DEFAULT",        -- "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE" 
		IDELAY_VALUE => 0,               -- Input delay tap setting (0-32)
		ODELAY_TYPE => "FIXED",          -- "FIXED", "VARIABLE", or "VAR_LOADABLE" 
		ODELAY_VALUE => 0,               -- Output delay tap setting (0-32)
		REFCLK_FREQUENCY => 200.0,       -- IDELAYCTRL clock input frequency in MHz
		SIGNAL_PATTERN => "DATA"         -- "DATA" or "CLOCK" input signal
	)
	port map (
		CNTVALUEOUT => open , -- 5-bit output - Counter value for monitoring purpose
		DATAOUT => data_delayed_s(j),       -- 1-bit output - Delayed data output
		C => Low,                     -- 1-bit input - Clock input
		CE => Low,                   -- 1-bit input - Active high enable increment/decrement function
		CINVCTRL => Low,       -- 1-bit input - Dynamically inverts the Clock (C) polarity
		CLKIN => Low,             -- 1-bit input - Clock Access into the IODELAY
		CNTVALUEIN => LowWord,   -- 5-bit input - Counter value for loadable counter application
		DATAIN => Low,	          -- 1-bit input - Internal delay data
		IDATAIN => adc_data_s(j) ,      -- 1-bit input - Delay data input
		INC => Low,                 -- 1-bit input - Increment / Decrement tap delay
		ODATAIN => Low,         -- 1-bit input - Data input for the output datapath from the device
		RST => rst, -- 10.1                -- 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
                                  -- ODELAY_VALUE tap. If no value is specified, the default is 0.
		T => High                      -- 1-bit input - 3-state input control. Tie high for input-only or internal delay or
                                  -- tie low for output only.

	);
	
   FF_inst : FDCE
        generic map (INIT => '0')
        port map (D => data_delayed_s(j), CE => not rst, C => dry_clk_2x, CLR => Low,
                  Q => ff_data(j));
						
end generate ADC_IN_GEN;



 -- 4. fpga clock from DAC


	-- -------------------buffer for fpga_clock from DAC------------------------------------------------
	IBUFGDS_inst2 : IBUFGDS
	generic map (
	DIFF_TERM => FALSE, -- Differential Termination
	IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards
	IOSTANDARD => "DEFAULT")
	port map (
		O => fpga_clk_s, -- Clock buffer output
		I => fpga_clk_inp, -- Diff_p clock buffer input (connect directly to top-level port)
		IB => fpga_clk_inn -- Diff_n clock buffer input (connect directly to top-level port)
	);

 process (led_1, led_2) begin
 if (led_1 = '1') and (led_2 = '1') then
  fifo_rst <= '0';
 else
	fifo_rst <= '1';
end if;

end process;

-- for write edge, if fifo_rst = 0 wr_en = 1 else wr_en = 0
 -- wr_en = wr_en
 
 process (dry_clk_2x) begin
 if (rising_edge(dry_clk_2x)) then
  if (fifo_rst = '0') then
		wr_en_in <= '1';
	else
		wr_en_in <= '0';
	end if;
else
	wr_en_in <= wr_en_in ;
end if;
end process;


process (data_clk) begin
 if (rising_edge(data_clk)) then
  if (fifo_rst = '0') then
		rd_en_in <= '1';
	else
		rd_en_in <= '0';
	end if;
else
	rd_en_in <= rd_en_in ;
end if;
end process;		


-- v2.10 ends
fifo_inst1 : fifo_generator_v9_3
  PORT MAP (
    rst => fifo_rst,
    wr_clk => dry_clk_2x,
    rd_clk => data_clk,
    din => ff_data,
    wr_en => wr_en_in,
    rd_en =>rd_en_in,
    dout => fifo_out,
    full => full,
    wr_ack => wr_ack,
    overflow => overflow,
    empty => empty,
    valid => valid,
    underflow => underflow
  );							
						
						
	---------------------------------------------- Idelay Control ----------------------------------------------------------------------
	
	IDELAYCTRL_inst : IDELAYCTRL
		port map (
			RDY => Ready_idelay_out, -- 1-bit output indicates validity of the REFCLK
			REFCLK => ref_clk200_bufg, -- 1-bit reference clock input
			RST	=> rst -- 10.1 -- 1-bit reset input
		);
	
	
MMCM_BASE_inst : MMCM_BASE
	generic map (
	BANDWIDTH => "OPTIMIZED", -- Jitter programming ("HIGH","LOW","OPTIMIZED")
	-- v 2.15 CLKFBOUT_MULT_F => 15.0, -- Multiply value for all CLKOUT (5.0-64.0).
	CLKFBOUT_MULT_F => 16.0, -- Multiply value for all CLKOUT (5.0-64.0). --2.15
	CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (0.00-360.00).
	
   CLKIN1_PERIOD => 10.416, -- v4.1 Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).(or 21.7 if input freq is 46.08 msps) or 86.8			
			-- 4 ns = 250 MHz Version 1.2
	CLKOUT0_DIVIDE_F => 2.0, --  Divide amount for CLKOUT0 (1.000-128.000). -- v2.15
	-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
	CLKOUT0_DUTY_CYCLE => 0.5, -- v2.14
	
	CLKOUT4_DUTY_CYCLE => 0.5,
	-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
	CLKOUT0_PHASE => 0.0, -- v2.14
	CLKOUT4_PHASE => 0.0,
	
		CLKOUT4_DIVIDE => 8, -- v2.15 -- v4.1
	CLKOUT4_CASCADE => FALSE, -- Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
	CLOCK_HOLD => FALSE, -- Hold VCO Frequency (TRUE/FALSE)
	-- v2.15 DIVCLK_DIVIDE => 5, -- Master division value (1-80)
	 DIVCLK_DIVIDE => 2, -- Master division value (1-80) -- v2.15 -- v4.1
	-- DIVCLK_DIVIDE => 4, -- Master division value (1-80) -- v2.15
						-- 5 so that 250 Mhz * (5/5) = 250 Mhz Version 1.2
	REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
	STARTUP_WAIT => FALSE -- Not supported. Must be set to FALSE.
	)

	port map (
	-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
	CLKOUT0 => clkout0pin, -- 1-bit output: CLKOUT0 output -- v2.14
	
	CLKOUT4 => clkout4pin, -- 1-bit output: CLKOUT0 output
	-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
	CLKFBOUT => CLKFBOUTpin, -- 1-bit output: Feedback clock output
	CLKFBOUTB => CLKFBOUTBpin, -- 1-bit output: Inverted CLKFBOUT output
	-- Status Port: 1-bit (each) output: MMCM status ports
	LOCKED => Led_2, -- 1-bit output: LOCK output
	-- Clock Input: 1-bit (each) input: Clock input
	CLKIN1 => fpga_clk_s,
	-- Control Ports: 1-bit (each) input: MMCM control ports
	PWRDWN => PWRDWN, -- 1-bit input: Power-down input
	RST =>  RST, -- 1-bit input: Reset input
	-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
	CLKFBIN => CLKFBINpin -- 1-bit input: Feedback clock input
	);


 ---------------------------------------------------Bufg for clkout0 ------------------------------------------------------------------
	-- version 1.1
	BUFG_inst_chip : BUFG
	port map (
	O => chip_780_clk, -- 1-bit output: Clock buffer output
	I => clkout0pin -- 1-bit input: Clock buffer input
	);

-- ---------------------------------------------------Bufg for fback ------------------------------------------------------------------
	-- version 1.1
	BUFG_inst : BUFG
	port map (
	O => clkfbinpin, -- 1-bit output: Clock buffer output
	I => clkfboutpin -- 1-bit input: Clock buffer input
	);


-- --------------------------------------------------- bufg for data_clk ------------------------------------------------------------------
	-- version 1.1
	BUFG_inst1 : BUFG
	port map (
	O => data_clk, -- 1-bit output: Clock buffer output
	I => clkout4pin -- 1-bit input: Clock buffer input
	);
	
	data_clk1<= data_clk;
						
	

		
counter_dataclk : counter1 port map (fpga_clk_s, led_out2, '0');
--counter_dataclk_2x : counter1 port map (dry_clk_2x, led_out3, '0');	
counter_dataclk_2x : counter1 port map (IO_DA(6), led_out3, '0');

 led_out (7 downto 5) <= led_out2 (7 downto 5);
 led_out (4 downto 2) <= led_out3(7 downto 5);
--led_out(7 downto 2) <= adc_data_s(7 downto 2);

led_out (1)	<= Led_2; -- fpga clock
led_out	(0) <= Led_1; -- write clock

-- 2.11 starts

IO_DA(15 downto 4) <= fifo_out;
IO_DA (3 downto 0) <= "0000";
	 --------------------------------- output buffer for outputs to DAC-------------------------------------------------------
	 IO_DA_GEN: for j in 0 to 15 generate
	 begin
	 OBUFDS_inst_IO_DA : OBUFDS
	 generic map (
	 IOSTANDARD => "DEFAULT")
	 port map (
		 O => IO_DAP(j),
		 OB => IO_DAN(j),
		 I => IO_DA(j)
	 );
	 end generate IO_DA_GEN;
	-- ----------------------------------------------output buffer for data clock1 -------------------------------------------------------
	OBUFDS_inst_dataclk : OBUFDS
	generic map (
	IOSTANDARD => "DEFAULT")
	port map (
		O => DATA_CLKP, -- Diff_p output (connect directly to top-level port)
		OB => DATA_CLKN, -- Diff_n output (connect directly to top-level port)
		I => DATA_CLK1 -- Buffer input
	);

	----------------------------------------------------------- output buffer for Parity-------------------------------------------------------
	OBUFDS_inst_sync_PARITY : OBUFDS
	generic map (
	IOSTANDARD => "DEFAULT")
	port map (
		O => PARITYP, -- Diff_p output (connect directly to top-level port)
		OB => PARITYN, -- Diff_n output (connect directly to top-level port)
		I => PARITY -- Buffer input
	);

	--sync <= not sync;
	-------------------------------------------------------------- output buffer for Sync-------------------------------------------------------
	OBUFDS_inst_sync : OBUFDS
	generic map (
	IOSTANDARD => "DEFAULT")
	port map (
		O => SYNCP, -- Diff_p output (connect directly to top-level port)
		OB => SYNCN, -- Diff_n output (connect directly to top-level port)
		I => SYNC -- Buffer input
	);

	--fifo_istr <= not fifo_istr;
 	-------------------------------------------------------------- output buffer for FIFO_ISTR-------------------------------------------------------
	OBUFDS_inst_FIFO : OBUFDS
		generic map (
	IOSTANDARD => "DEFAULT")
	port map (
		O => FIFO_ISTRP, -- Diff_p output (connect directly to top-level port)
		OB => FIFO_ISTRN, -- Diff_n output (connect directly to top-level port)
		I => FIFO_ISTR -- Buffer input
	);
	
	-------------------- output buffer for sma_out to ADC clock ------------------
	-- 1.3
	OBUFDS_inst_sma : OBUFDS
		generic map (
		IOSTANDARD => "DEFAULT")
		port map (
			O => sma_outp, -- Diff_p output (connect directly to top-level port)
			OB => sma_outn, -- Diff_n output (connect directly to top-level port)
			I => data_clk -- Buffer input
		);	
	

-- 2.11 ends 
	
	
end Behavioral;

0143.ucf.txt

# 2.11 starts
NET "IO_DAP[15]" IOSTANDARD = LVDS_25;
NET "IO_DAP[14]" IOSTANDARD = LVDS_25;
NET "IO_DAP[13]" IOSTANDARD = LVDS_25;
NET "IO_DAP[12]" IOSTANDARD = LVDS_25;
NET "IO_DAP[11]" IOSTANDARD = LVDS_25;
NET "IO_DAP[10]" IOSTANDARD = LVDS_25;
NET "IO_DAP[9]" IOSTANDARD = LVDS_25;
NET "IO_DAP[8]" IOSTANDARD = LVDS_25;
NET "IO_DAP[7]" IOSTANDARD = LVDS_25;
NET "IO_DAP[6]" IOSTANDARD = LVDS_25;
NET "IO_DAP[5]" IOSTANDARD = LVDS_25;
NET "IO_DAP[4]" IOSTANDARD = LVDS_25;
NET "IO_DAP[3]" IOSTANDARD = LVDS_25;
NET "IO_DAP[2]" IOSTANDARD = LVDS_25;
NET "IO_DAP[1]" IOSTANDARD = LVDS_25;
NET "IO_DAP[0]" IOSTANDARD = LVDS_25;



#2.8 #2.11
NET "DATA_CLKP" IOSTANDARD = LVDS_25;
#2.8 #2.11
NET "FIFO_ISTRP" IOSTANDARD = LVDS_25;
#2.8
NET "fpga_clk_inp" IOSTANDARD = LVDS_25;
#2.8 #2.11
NET "PARITYP" IOSTANDARD = LVDS_25;
#2.8 #2.11
NET "SYNCP" IOSTANDARD = LVDS_25;
#2.8 #2.11
NET "sma_outp" IOSTANDARD = LVDS_25;
#2.8 #2.11
NET "sma_outn" IOSTANDARD = LVDS_25;


NET "IO_DAP[0]" LOC = AN30;
NET "IO_DAP[1]" LOC = AN29;
NET "IO_DAP[2]" LOC = AN25;
NET "IO_DAP[3]" LOC = AM23;
NET "IO_DAP[4]" LOC = AM22;
NET "IO_DAP[5]" LOC = AK21;
NET "IO_DAP[6]" LOC = AF19;
NET "IO_DAP[7]" LOC = AC20;
NET "IO_DAP[8]" LOC = AH23;
NET "IO_DAP[9]" LOC = AL29;
NET "IO_DAP[10]" LOC = AL28;
NET "IO_DAP[11]" LOC = AN28;
NET "IO_DAP[12]" LOC = AP27;
NET "IO_DAP[13]" LOC = AK23;
NET "IO_DAP[14]" LOC = AP22;
NET "IO_DAP[15]" LOC = AM21;
#2.8 2.11
NET "DATA_CLKP" LOC = AH25;
#2.8 2.11
NET "FIFO_ISTRP" LOC = AG25;
#2.8 2.11
NET "FIFO_ISTRN" LOC = AG26;
#2.8
NET "fpga_clk_inp" LOC = K24;
NET "fpga_clk_inn" LOC = K23;
#2.8 2.11
NET "PARITYP" LOC = AK27;
#2.8 2.11
NET "SYNCP" LOC = AJ24;
#2.8 2.11
NET "sma_outp" LOC = V34;
#2.8 2.11
NET "sma_outn" LOC = W34;
#2.8NET "LED" LOC = AC22;
#2.8NET "LED" IOSTANDARD = LVCMOS25;
# 2.11 ends
NET "rst" LOC = A19;
NET "rst" IOSTANDARD = LVCMOS25;

# 2.11 starts
#NET "fifo_rst" LOC = A18;#2.8  pushbutton SW6
#NET "wr_en_in" LOC = H17;#2.8  SW8
#NET "rd_en_in" LOC = G17;#2.8 SW7
#
#NET "fifo_rst" IOSTANDARD = LVCMOS25;#2.8
#NET "wr_en_in" IOSTANDARD = LVCMOS25;#2.8
#NET "rd_en_in" IOSTANDARD = LVCMOS25; #2.8
# 2.11 ends
##NET "led_clk" LOC = AC24;
## led 0 - DS12	#2.8
NET "led_out[0]" LOC = AC22;
NET "led_out[1]" LOC = AC24;
NET "led_out[2]" LOC = AE22;
NET "led_out[3]" LOC = AE23;
NET "led_out[4]" LOC = AB23;
NET "led_out[5]" LOC = AG23;
NET "led_out[6]" LOC = AE24;
## led 8 - DS21
NET "led_out[7]" LOC = AD24;
#NET "led_clk" IOSTANDARD = LVCMOS25;
#2.8
NET "led_out[0]" IOSTANDARD = LVCMOS25;
NET "led_out[1]" IOSTANDARD = LVCMOS25;
NET "led_out[2]" IOSTANDARD = LVCMOS25;
NET "led_out[3]" IOSTANDARD = LVCMOS25;
NET "led_out[4]" IOSTANDARD = LVCMOS25;
NET "led_out[5]" IOSTANDARD = LVCMOS25;
NET "led_out[6]" IOSTANDARD = LVCMOS25;
NET "led_out[7]" IOSTANDARD = LVCMOS25;
## ADC pin out
#NET "adc_inp[0]" LOC = J31;
#NET "adc_inn[0]" LOC = J32;
#NET "adc_inp[1]" LOC = J30;
#NET "adc_inn[1]" LOC = K29;
NET "adc_inp[11]" LOC = G32;
NET "adc_inn[11]" LOC = H32;
NET "adc_inp[10]" LOC = E32;
NET "adc_inn[10]" LOC = E33;
NET "adc_inp[9]" LOC = D31;
NET "adc_inn[9]" LOC = D32;
NET "adc_inp[8]" LOC = A33;
NET "adc_inn[8]" LOC = B33;
NET "adc_inp[7]" LOC = C32;
NET "adc_inn[7]" LOC = B32;
NET "adc_inp[6]" LOC = M30;
NET "adc_inn[6]" LOC = N30;
NET "adc_inp[5]" LOC = P29;
NET "adc_inn[5]" LOC = R29;
NET "adc_inp[4]" LOC = N27;
NET "adc_inn[4]" LOC = P27;
NET "adc_inp[3]" LOC = R26;
NET "adc_inn[3]" LOC = T26;
NET "adc_inp[2]" LOC = N32;
NET "adc_inn[2]" LOC = P32;
NET "adc_inp[1]" LOC = P31;
NET "adc_inn[1]" LOC = P30;
NET "adc_inp[0]" LOC = C33;
NET "adc_inn[0]" LOC = B34;
#NET "adc_inp[0]" LOC = N33;
#NET "adc_inn[0]" LOC = M33;

#NET "ovr_inp" LOC = J30;
#NET "ovr_inn" LOC = K29;

NET "dry_clk_inp" LOC = N28;
NET "dry_clk_inn" LOC = N29;
NET "SYSCLK_P" LOC = J9;
NET "SYSCLK_N" LOC = H9;
NET "dry_clk_inp" CLOCK_DEDICATED_ROUTE = FALSE;
NET "dry_clk_inn" CLOCK_DEDICATED_ROUTE = FALSE;

NET "adc_inp[0]" IOSTANDARD = LVDS_25;
NET "adc_inn[0]" IOSTANDARD = LVDS_25;
NET "adc_inp[1]" IOSTANDARD = LVDS_25;
NET "adc_inn[1]" IOSTANDARD = LVDS_25;
NET "adc_inp[2]" IOSTANDARD = LVDS_25;
NET "adc_inn[2]" IOSTANDARD = LVDS_25;
NET "adc_inp[3]" IOSTANDARD = LVDS_25;
NET "adc_inn[3]" IOSTANDARD = LVDS_25;
NET "adc_inp[4]" IOSTANDARD = LVDS_25;
NET "adc_inn[4]" IOSTANDARD = LVDS_25;
NET "adc_inp[5]" IOSTANDARD = LVDS_25;
NET "adc_inn[5]" IOSTANDARD = LVDS_25;
NET "adc_inp[6]" IOSTANDARD = LVDS_25;
NET "adc_inn[6]" IOSTANDARD = LVDS_25;
NET "adc_inp[7]" IOSTANDARD = LVDS_25;
NET "adc_inn[7]" IOSTANDARD = LVDS_25;
NET "adc_inp[8]" IOSTANDARD = LVDS_25;
NET "adc_inn[8]" IOSTANDARD = LVDS_25;
NET "adc_inp[9]" IOSTANDARD = LVDS_25;
NET "adc_inn[9]" IOSTANDARD = LVDS_25;
NET "adc_inp[10]" IOSTANDARD = LVDS_25;
NET "adc_inn[10]" IOSTANDARD = LVDS_25;
NET "adc_inp[11]" IOSTANDARD = LVDS_25;
NET "adc_inn[11]" IOSTANDARD = LVDS_25;
NET "dry_clk_inp" IOSTANDARD = LVDS_25;
NET "dry_clk_inn" IOSTANDARD = LVDS_25;
NET "SYSCLK_P" IOSTANDARD = LVDS_25;
NET "SYSCLK_N" IOSTANDARD = LVDS_25;

#NET "ovr_inp" IOSTANDARD = LVDS_25;
#NET "ovr_inn" IOSTANDARD = LVDS_25;



# 2.11 : 11:40 pm 06 May
#  -- This file is being used in adc_to_dac_1 project directory
#  -- adc -> fpga -> dac is being written
#  -- March 18 entry
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/05/07
NET "dry_clk_inn" TNM_NET = "dry_clk_inn";
TIMESPEC TS_dry_clk_inn = PERIOD "dry_clk_inn" 20.833 ns HIGH 50 %;
NET "dry_clk_inp" TNM_NET = "dry_clk_inp";
TIMESPEC TS_dry_clk_inp = PERIOD "dry_clk_inp" 20.833 ns HIGH 50 %;
NET "fpga_clk_inn" TNM_NET = "fpga_clk_inn";
TIMESPEC TS_fpga_clk_inn = PERIOD "fpga_clk_inn" 10.416 ns HIGH 50 %;
NET "fpga_clk_inp" TNM_NET = "fpga_clk_inp";
TIMESPEC TS_fpga_clk_inp = PERIOD "fpga_clk_inp" 10.416 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/05/07
INST "adc_inn[0]" TNM = "data_in";
INST "adc_inn[1]" TNM = "data_in";
INST "adc_inn[2]" TNM = "data_in";
INST "adc_inn[3]" TNM = "data_in";
INST "adc_inn[4]" TNM = "data_in";
INST "adc_inn[5]" TNM = "data_in";
INST "adc_inn[6]" TNM = "data_in";
INST "adc_inn[7]" TNM = "data_in";
INST "adc_inn[8]" TNM = "data_in";
INST "adc_inn[9]" TNM = "data_in";
INST "adc_inn[10]" TNM = "data_in";
INST "adc_inn[11]" TNM = "data_in";
INST "adc_inp[0]" TNM = "data_in";
INST "adc_inp[1]" TNM = "data_in";
INST "adc_inp[2]" TNM = "data_in";
INST "adc_inp[3]" TNM = "data_in";
INST "adc_inp[4]" TNM = "data_in";
INST "adc_inp[5]" TNM = "data_in";
INST "adc_inp[6]" TNM = "data_in";
INST "adc_inp[7]" TNM = "data_in";
INST "adc_inp[8]" TNM = "data_in";
INST "adc_inp[9]" TNM = "data_in";
INST "adc_inp[10]" TNM = "data_in";
INST "adc_inp[11]" TNM = "data_in";
TIMEGRP "data_in" OFFSET = IN -0.25 ns VALID 10.1665 ns BEFORE "dry_clk_inp" RISING;
TIMEGRP "data_in" OFFSET = IN -0.25 ns VALID 10.1665 ns BEFORE "dry_clk_inp" FALLING;
TIMEGRP "data_in" OFFSET = IN -0.25 ns VALID 10.1665 ns BEFORE "dry_clk_inn" RISING;
TIMEGRP "data_in" OFFSET = IN -0.25 ns VALID 10.1665 ns BEFORE "dry_clk_inn" FALLING;

Thank you

Pramod singh

Data converters

Data converters forum

Interfacing of virtex-6 FPGA board with DAC34SH84 and ADS54RF63