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DAC5675A Weak SFDR and Odd Harmonics

Other Parts Discussed in Thread: DAC5675A

Hi,

I have designed data conversion card with DAC5675A, 

Description :

FPGA Design was Altera NCO’s IP core to generate 20.1 MHz sinusoidal at 400MHz sampling rate. 400MHz. clock is generated from Altera PLL and apply to DAC for sampling. Output measured in frequency domain

Issue # 1

As per Datasheet Spurious-free dynamic range should be 73 dBc @ Fclk = 400MSPS, F out = 20.1MHz.

But Practically I am getting 52.11dBc

Issue : 2

Fundamental frequency component at -3.19dBm & Level of First Harmonic is much higher.

Please Find Attached Copy of Schematic of DAC section + Power & System Overview

sch_hsmcdc4m_1504_b1a_02.pdf

Thanks

Harsh

  • Hi Harsh,

    I have to look at the circuit schematic to give you more info. Can you please send me circuit schematic?

    Regards,
    Neeraj
  • Hi Neeraj,

    Thanks for quick response,

    Please find copy of schematic of DAC section + Power & System Overview

    Thanks & Regards
    Harsh
  • Hi Harsh,

    Make sure you are not saturating the spectrum analyzer while taking the measurement. Try increasing the RF attenuation level on the spectrum analyzer and see if you observe any improvements in the results.

    I have attached the screen shots taken at different attenuation levels


    Figure 1 Att is 5dBm and SFDR is 57.54 dBc

    Figure 2 Att is 10dBm and SFDR is 62.11 dBc

     Figure 3 Att is 25dBm and SFDR is 71.64 dBc

    If don't see any improvement in the results. 

     

    I think following might be the case. 

    The 2nd harmonic spurs are usually related to differential balancing of the circuit. In other words design (layout) being not optimized for differential signals.

    The other spurs are probably caused by timing and data not setup properly. Make sure you are meeting timing parameter shown in datasheet on page 6 in digital specifications table.

    Regards,

    Neeraj