Hi,
I have designed data conversion card with DAC5675A,
Description :
FPGA Design was Altera NCO’s IP core to generate 20.1 MHz sinusoidal at 400MHz sampling rate. 400MHz. clock is generated from Altera PLL and apply to DAC for sampling. Output measured in frequency domain
Issue # 1
As per Datasheet Spurious-free dynamic range should be 73 dBc @ Fclk = 400MSPS, F out = 20.1MHz.
But Practically I am getting 52.11dBc
Issue : 2
Fundamental frequency component at -3.19dBm & Level of First Harmonic is much higher.
Please Find Attached Copy of Schematic of DAC section + Power & System Overview
Thanks
Harsh