DAC37J84EVM

John Reyland62

Intellectual 375 points

Other Parts Discussed in Thread: DAC37J84, LMK04828

Is this the correct procedure for synchronizing two DAC37J84 EVMs (call them A and B) connected to

the two high pin count FMC connectors on the Xilinx Virtex 7, VC707 eval. card.

Referring to the DAC37J84 EVM schematic, seems like the following steps are needed:

1. Remove R16 and R18 from EVM A (This disconnects the LMK 04828 DACCLK).

2. Connect J1 and J3 on EVM A to J1 and J3 on EVM B (drives DACCLK from B to A)

3. Remove R4 and R7 from EVM A. (This disconnects the LMK 04828 SYSREF).

4. Connect J5 and J7 from EVM A to B (drives SYSREF from B to A)

Now EVM B is controlling DACCLK and SYSREF on EVM A

The FPGA will need LMK04828 DCLKOUT0 on FMC B to synch the JESD204 timing

Does this seem correct? Has anyone actually done this?

Thanks very much, John Reyland

over 8 years ago

0 Kang Hsia over 8 years ago

TI__Guru 66184 points

John,

This seems feasible. I am concerned about the SYSREF delay that you will need to implement due to additional delay from the cable. You may need to adjust LMK04828 SYSREF delay accordingly to get this going. There is also the issue of not able to provide FPGA clock to the FMC port.

We have also come up with a way to use LMK04828's 0-delay PLL mode to provide a common, phase matched SYSREF signal to both EVMs. I will have to provide details with you at a later time.

-Kang

0 John Reyland62 over 8 years ago in reply to Kang Hsia

Intellectual 375 points

Thanks very much Kang. I will let you know if this works. John Reyland

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DAC37J84EVM