Dear
Can you please suggest me any Xilinx IP core compatible with Altera Megafunction ALTLVDS_RX and ALTPLL. I am configuring ADS4249 with Xilinx VC 707 kit. After going through FPGA Firmware Example of How To Interface Altera FPGAs to High-Speed LVDS-Interface Data Converters TIDA-00069 , I need Xilinx IP Core for Altera megafunctions used in the example code.
Best Regards
FRK
Hi,
That TI Design shows an example of using the Altera functions to implement the interface to our LVDS data converters, both ADC and DAC, and this TI Design made use of the work done in our TSW1400 capture card that is used in conjunction with our ADC and DAC EVMs. We do not have a similar design built around the Xilinx functions. We did have the older TSW1200 capture card that would interface with the LVDS ADC EVMS, including the ADS4249 that you mention, but we did not turn that code into a TI Design. The Xilinx functions that we used in the TSW1200 (built around the Virtex4) was the IDDR cell and the IDELAY cell. Below is a sketch of how the IDDR cell and IDELAY cells are used to implement the ADC interface. The IDDR cell latches the incoming DDR data on the rising and falling edges of the LVDS clock, and the IDELAY cell is used to add delay to either the clock or data as needed to meet setup/hold timing into the IDDR cell. in your design, you would need to use the Xilinx static timing analysis tools to determine what IDELAY setting you would need to close timing as the timing would be specific to your Virtex7 FPGA that you would be using. If you provide an email address then I can send the source code from the TSW1200 as an example to look at.
Regards,
Richard P.
as stated in Datasheet of ADS4249 "
Even data bits (D0, D2, D4, and so forth) are output at the CLKOUTP rising edge and the odd data bits (D1, D3,
D5, and so forth) are output at the CLKOUTP falling edge Both the CLKOUTP rising and falling edges must be used to capture all the data bits,." my question is that we not used only rising edge or only falling for catpure all data bits. why we even at one edge and odd at other .Thanks
Dear Jim,
Thanks for your kind reply,
It means that I should use one IBUFDS each for every data and clock differential pairs to make it one bit output and so on for every 7 differential data pairs, and then we should receive our data on each raising and falling edges of clock like in the picture that i have attached.
and yes I am using one ADC and I am using its channel A only.
and one more thing, you have provided me a link for parallel interface in your early post (4213.Interfacing to FPGA's app note.pdf) but after going through i have found that there is description for serial interface in that document, can you suggest something for parallel interface.
Thanks and Regards
FRK,
See if this attachment helps. Also below is from an old post to another customer with a similar issue.
Hi,
That TI Design shows an example of using the Altera functions to implement the interface to our LVDS data converters, both ADC and DAC, and this TI Design made use of the work done in our TSW1400 capture card that is used in conjunction with our ADC and DAC EVMs. We do not have a similar design built around the Xilinx functions. We did have the older TSW1200 capture card that would interface with the LVDS ADC EVMS, including the ADS4249 that you mention, but we did not turn that code into a TI Design. The Xilinx functions that we used in the TSW1200 (built around the Virtex4) was the IDDR cell and the IDELAY cell. Below is a sketch of how the IDDR cell and IDELAY cells are used to implement the ADC interface. The IDDR cell latches the incoming DDR data on the rising and falling edges of the LVDS clock, and the IDELAY cell is used to add delay to either the clock or data as needed to meet setup/hold timing into the IDDR cell. in your design, you would need to use the Xilinx static timing analysis tools to determine what IDELAY setting you would need to close timing as the timing would be specific to your Virtex7 FPGA that you would be using. If you provide an email address then I can send the source code from the TSW1200 as an example to look at.
Regards,
Richard P.
