ADC14X250: JESD204B over fiber

Hi Satish,
The "JOOS demo" link provided by Jim in the original question, attached below, does not work anymore.
I could not find it online in TI videos, could you please help me find this demo?
http://www.ti.com/general/docs/video/watch.tsp?entryid=drupal:7.x:3980:31d555187c3bc08a5dc0003ac675c200&keyMatch=ims2015%20joos&tisearch=Search--Everything

And couple more questions from the original thread:

1. Jim mentions while explaining clock: "If multi-converter synchronization or deterministic latency are not required then SYSREF may be optional for some devices. Several of the TI ADC products can operate without SYSREF in these scenarios." - Does this apply to ADC14X250? Can this product work without SYSREF if multi-converter sync and deterministic latency are not required?

 2. Explaining the data transfer Jim also mentions that - "It is possible to aggregate multiple JESD204B lanes into a single optical link. This is done in the JOOS demo, where multiple 10Gbps channels from the ADCs and for the DACs are combined and sent over a single optical link. " - Can I aggregate JESD204B lane signals with clock signals and send it over one link? Why do I need separate link for clocks if signals can be aggregated

Thank you
Lizon

Hi Lizon,

Here is a link location for the video: https://training.ti.com/ims2015-joos-demo. 

Best,
Mark

Hi Mark,

So it says access denied, the screen shot is attached with this message.

Also I had a couple of questions, 

1. Jim mentions while explaining clock: "If multi-converter synchronization or deterministic latency are not required then SYSREF may be optional for some devices. Several of the TI ADC products can operate without SYSREF in these scenarios." - Does this apply to ADC14X250? Can this product work without SYSREF if multi-converter sync and deterministic latency are not required?

 2. Explaining the data transfer Jim also mentions that - "It is possible to aggregate multiple JESD204B lanes into a single optical link. This is done in the JOOS demo, where multiple 10Gbps channels from the ADCs and for the DACs are combined and sent over a single optical link. " - Can I aggregate JESD204B lane signals with clock signals and send it over one link? Why do I need separate link for clocks if signals can be aggregated

Thank you
Lizon

Hi Matt,

Thank you.

The first answer solves a big question that I had about retrieving the embedded clock.

But if deterministic latency is not a requirement for my application, and If I am trying to use only one ADC, can I ignore SYSREF? I believe this is not possible because I cannot establish the link without SYSREF in JESD204B subclass 2 - Am I correct here?  (ADC14x250EVM --> TSW14J56). So, what if I create SYSREFs using independent device clock signals (same frequency but not phase locked) and LMK04828s in each side, this should allow me to establish the link, but det. latency wouldn't be there, which I don't care about. I have included a block diagram for reference.

I am having a hard time following this sentence: " For instance, in a 12-fiber device, we may use 4 lanes for JESD204B data and 1 lane for clocks." By 12-fiber device, you mean 12 fiber links?  4 lanes of JESD204B data, meaning sending data from each converter separately? And 1 lane for clocks meaning - you are sending Device clock, Sync and SYSREF all through 1 fiber link, isn't that aggregating then? In your JOOS demo,  you have used 4 fiber links between the ADC/DAC transceiver group and FPGAs, what are you sending through each one of these?

Regards,  

Lizon

Hi Lizon,

In the case where SYSREF is required, I think your scheme will work. You may be able to get away without SYSREF, but each device is different and I don't know if the ADC14X250 has any potential problems without SYSREF. I'm guessing it's fine, however what you've shown would be the "safe" implementation. Then you can always try disabling SYSREF to see if the system still comes up properly (must be testing many times to catch the various phases that clocks could come up in). You're right that deterministic latency is not guaranteed with this method. The only concern is making sure that the multi-frame period is small enough that your elastic buffer won't overflow (e.g. set K to the lowest possible value, with condition that F*K >= 17). This will also limit the latency variation you have from startup to startup.

In the JOOS demo, there were data lines (4 in each direction per ADC/DAC = 8 total in each direction) and a SYSREF sent back to the FPGAs from the data converter side of the link. SYSREF provided both a phase and a timing reference, which was used with the zero-delay mode of the LMK04828 to generate a phase locked SYSREF and a synchronous core clock (around 250 MHz) for the FPGA. In additional there was an 8B/10B encoded signal in each direction (over another optical link) in order to transmit the JESD204B SYNC signal used for link initialization (start CGS and ILAS process).

Regards,
Matt Guibord