DAC8760 Schematic Verification

Hello,

It sounds like you're familiar with at least one of the TI Designs related to the DAC8760 - there are several floating around ti.com from various groups within TI. The TI Design (tidu392.pdf) you mentioned uses one approach to deliver IEC61000-4 protection for the DAC8760, similar content is discussed in TI Precision Design 153 (www.ti.com/tool/tipd153/). I mention TIPD153 because this design uses fewer components for the external protection circuit while still achieving good accuracy and surviving the IEC61000-4 transients (also maybe I'm a little biased as I worked on TIPD153 myself).

TIPD153 goes into a some high-level details concerning the concept behind the structure of the protection circuit, if you'd like to hear more about "what we were thinking" when the structure was designed feel free to ask and I'll try to explain further. The document also explains exactly what IEC61000-4 tests and corresponding threat levels were applied to the design. As I'm sure you're aware, each of the IEC61000-4 tests can vary in threat level - usually this just means variance in the voltage magnitude of the transient but in cases like surge both voltage and transient source generator output impedance change. As these parameters of the transients change, the protection circuit too may need to change. More specifically, the circuit that is shown in IEC61000-4 does a good job at protecting the DAC8760 and realizing "criteria A" performance for most of the IEC61000-4 tests and the circuit doesn't need to change much (if at all) as ESD, EFT, CI, or RI threat levels change. In the case of surge testing, however, you may have to vary the circuit some. The circuit discussed in TIPD153 will suffice for 1.0kV w/47ohm output impedance but will need some changes, either in component selection or in fundamental structure, in order to achieve a passing result for higher voltage or lower output impedance tests. Again if you have any specific questions please let us know and we'll try to clarify for you.

Concerning the capacitor on the HART input pin, this is not functionally required as Eugenio mentioned. However, this is a high-impedance input node directly into the current output signal chain inside of the DAC8760. That means there is possibility for radiated or conducted emissions to couple to the current output which is often not desirable (things you might observe during IEC61000-4 conducted and radiated immunity tests). The capacitor was included to AC couple any radiation, that may have otherwise made its way to the current output, to GND. I would suggest you keep the capacitor - as you'll see in TIPD153 which included this capacitor the extra routing required to connect VSENSE+ to VOUT is not significant enough to degrade performance outside of datasheet parameters. TIPD153 includes a layout example, for DC performance and for IEC61000-4 transient immunity I would suggest that you follow at least a similar layout.

You mentioned pull-ups and series resistors on digital I/O lines - I think Eugenio covered the series resistors. Though I don't think it's covered in TIPD153 or the other TI Designs, including a pull-up resistor on the LATCH pin is sometimes advisable in order to prevent any "random" data from being latched into the SPI interface during power-up (maybe random signals come from the MCU during start-up etc.).

I think you mentioned an interest in an ADC for system feedback and consultation in selecting that ADC. If you could elaborate on exactly what system feedback means we can provide some suggestions / comments for that as well.

Dear Eugenio and Kevin,

Thank you for your consultation and help related with DAC8760, After placing our samples from TI to DAC pcb that I layout, We prove the system works great. We only have some noise on output from SPI channel (even we have separated grounds). 

We consider using another pcb package for DAC8760 that have more cap input pins.

After some revision we will place mass production. How could you check pcb side of our work after the last revision for the SPI noise side consultation? which format should I send the PCB layout to you. We use KiCAD for sch and layout. 

Thank you again, We appreciate with your solutions.

Best Regards.

Sarper,

I am very glad to hear you are pleased with both the device performance and our support. Thanks for passing on the praise, it's always nice to receive feedback.

I would be happy to review the layout. We use Altium in TI which has some import utilities, I've never tried importing from KiCAD but we can give it a shot. As a back-up I could look at the raw Gerber files, though this is usually less desirable as it's more difficult to navigate the layout. We will figure something out.

If you would like to keep your schematic and layout confidential, feel free to send me a private message on the E2E Community and we can exchange email addresses to discuss the review.