Synchronized sampling using ADS1262

Hi jxu,

Welcome to the TI E2E forums!

The conversion latency will be within td(STDR) + 8/f(CLK). In other words, you may see an additional delay of up to 8 master clock (7.3728MHz) cycles. The reason for this delay is that the modulator runs off of the mod clock, which is 1/8th the frequency of the master clock. When issuing a START command, the command may take place either within the current mod clock period or the next.

Resetting the devices to improve synchronization

Likely, the mod clocks are starting slightly out-of-sync after powering up the devices. If you have the ability, you could issue a hardware reset (using a shared RESET pin) to all four ADCs to restart the mod clocks and improve the synchronization. To ensure that all the resets take place within the same clock period, you would want the RESET signal to transition during a master clock falling edge (so take RESET low on a falling clock edge, wait at least 4 clock periods, and take RESET high during another falling clock edge).

Alternatively, if all four ADCs share the same SCLK signal, and SCLK is derived from the master clock, you may be able to issue a software RESET command to synchronize the mod clocks. However, again to ensure that the commands all take place within the same master clock period, the falling edge of SCLK must align with the rising edge of the master clock.

Both of these methods require very strict timing to truly synchronize the ADC clocks; regardless, you might still see some improvement in synchronization by  resetting the devices after power-up, even without adhering to this level of timing.

Best regards,
Chris