[TVP5158] Do you have recommend register setting for PAL mode operation with non-interleved mode?

Please check that the correct decoder is being used for I2C read/write operation in registers FEh and FFh.  If this this looks OK, then check the input signal and signal path to the TVP5158.

Hello Phunjapa,

Please check the register 0x01, if bit 7 is not 1 then there is no signal input to the TVP5158.  If there is no signal, the device is default to NTSC.

Regards,

Viet

The register 0x01 is 0xf8, I wonder why bit[6] is '1' that means weak signal detect? Does it means that input path of TVP5158 have low quality signal?

This is my environment.

1) Video input is generated from Pattern Generator with PAL system

2) TVP5158 schematic, we copy same design with TVP5158 evaluation platform (referred to sleu108.pdf page 38 - page 41)

3) I2C is programmed by FPGA

4) All video data output is fed to FPGA to process

----------------------------------------------------------

[1] After I2C programming, I write I2C register @ B2h = 25h

Then, read I2C register @ 01h to video signal input status. Read value = F8h which means that signal is present, but weak signal.

Read I2C register @ 0Ch to check video mode from auto-detect. Read value = 01h which means that video input is NTSC system, not PAL.

Do you have any commend that why video decoder detect PAL input signal from pattern generator that is NTSC, not PAL?

[2] I try to force video decoder to run in PAL mode by writing I2C register @ 0Dh = 02h.

Then, read I2C register @ 00h to check video decoder status. Read value = 70h which means that cannot lock HSYNC and VSYNC.

Is this video decoder required more register setting to run PAL system correctly?

[3] From evaluation schematic,

- What's R32 (1 Mohm) function? Should it add in circuit? 

- R106 is 0 ohm to connect between crystal and AGND. From "sleu108.pdf: PCB Layout Guidelines", it's recommended to add R 0 ohm to provide flexibility to crystal reference connection. What's function? Do we need to adjust this resistor to other value? 

Best Regards,

Phunjapa.

Phunjapa,

Make sure that Pin82 is pulled to logic low level.  The TVP5158 can enter a test mode if this is not done.

The TVP5158 should report locked state if a valid signal is present at the input of the docoder being used, without special I2C setup.

The R32 1M resistor is not requried.  R106 adjustment is not required, it is a connection to ground.

Do signal levels look good at the TVP5158 video input?

Do all power supply levels look good?

If you enable OCLK_P in REG82h, do you see a 27Mhz clock output on OCLK_P?

Can you send your schematics?

Hi Larry Taylor,

I see the clock 27MHz and OCLK_P when set register 0xb2 = 0x25. 

Using Oscilloscope to check , power supply and video input signal look good like as attach image . 

And the pin 82 is connected to Digital GND as schematic.

Do you have any comment to check, why signal is not locked?

However, I found some strange in below test environment, too..

[Test envinroment]

1.I don't insert Video Signal input

2. After power on, set register 0xb2 = 0x25 only,

[Result]

1. Register 0x00 = 0x10, Register 0x01 = 0xf8 / 0xe8 / 0xc8

2. FPGA can see data from PortA output including preamble code but signal is incorrect sync (I can not count line correctly). 

Question,

1. Why TVP5158 have output at port A even though don't have input video signal? Is it normal?

8741.CaptureBoard.pdf

4667.SignalMeasure.zip

Phunjapa,

REG01h weak signal detection points to a noisy input or a problem with the TVP5158 circuit.  Have you tried another board or another video channel on the TVP5158?  It is possible that you have solder problem or a damaged TVP part.. 

I would foucs now on using a standard video source and try both PAL and NTSC signals to see if the behavior is the same.  Once this works reliably, then try the camera.  I did not see a scope capture of the vdieo input, but your input circuitry to the TVP5158 on the schematic looks OK.

The output port can output embedded sync and data with no input connected.  I would not try capture video until the TVP is reporting a good locked state.

Hi Larry,

We have 2 boards and the behavior is same. Now I would like to know that the below is abnormal and means that TVP is damaged or not, please suggest me.

After power on, Even though I don't insert input standard video signal (From pattern generator), Register 0x01 shows that Signal is present (bit-7 is '1'), Is this abnormal?

Phunjapa,

With no signal connected, my board reports "Signal Not Present" after power-up.  Have you checked the /Reset signal to make sure the TVP is being properly reset after power up?

Hi Larry,

Yes, I already check signal /Reset by oscilloscope. After power up, I force /Reset to be Low then High manually, (/Reset siganl  is output of IC RESET which its input signal is force by FPGA).So the /Reset signal is low more than in specification surely.

[1]. Could you suggest me the below step to check TVP5158 is suitable or not?

1. Power up boards

2. Forec /Reset then release

3. Write I2C @0xb2 to be 0x25

4. Write I2C @0x0d to be 0x02 to be PAL video input supported (I already check with TV that source is PAL)

3. Read I2C @0x01 to check that bit-7 is '1' or not

4. Read I2C @0x00 to check that bit-2, bit-1 shall be always '1' to shows that VSync and HSync is locked or not.

I should be check until both register output is OK as 3 and 4 then go other operation, right?

Hi Larry,

I already found and fixed my problem. I forgot to assembly Resistor at pin 116 (REXT_2K). Now I can solve it!!!.