120MHz & 150MHz Clock Settings for C5515 ezdsp?

Hi

For 120MHz:

PLL_CNTL2 = 0x616E;
PLL_CNTL4 = 0x0001;
PLL_CNTL3 = 0x0806;
PLL_CNTL1 = 0x8E48;

For 150MHz, it must use external clock. This example uses 12MHz.

PLL_CNTL2 = 0x613D;
PLL_CNTL4 = 0x0001;
PLL_CNTL3 = 0x0806;
PLL_CNTL1 = 0x8F7B;

Regards,

Hyun

Hyun,

I am a little confused by your values.

1. If you set PLL_CNTL2 = 0x616E, you are setting 14-12 to 0x110, which are reserved bits according to page 30 of SPRUFX5D. Is this correct?

2. As I mentioned, I am using the C5515 ezdsp, which uses the RTC clock (32768Hz) as its PLL input clock. Your values for 120MHz do not appear to the 32khz clock. Do they?

3. Why do I need to use an external clock to achieve 120MHz? Why can't I multiply 32khz by 3662 to achieve 119,996,416 Hz (120MHz)?

====================================== update =================

Never mind. I got it working.

Mikeh,

     Can you please tell me how are you checking PLL frequency is 100 MHz or 120 MHz.

Thanks

Santosh,

I use two methods.

1. Since I am using the C5515 ezdsp, there is a test point that I can put a scope on to see the clock. The clock period for 100MHz is 10ns. The clock period for 120MHz is 8.3ns.

2. I measure the execution time of an algorithm running on my board. I have measured its period to be ~1.3ms at 100MHz. When I change to 120MHz, its period drops to ~1.08ms.

I hope this help.

Mikeh,

      Thanks a lot.

      In your second method , how are you calculating execution time of the algorithm. Is there any option in Code composer studio to calculate execution time.

Thanks.

Santosh,

In the past I have used TI's DSP/BIOS in an attempt measure the duration of execution of code segments and algorithms. But it is quite complex and somewhat buggy leading to a lot of wasted time and frustration. Now I simply toggle extra GPIO lines and monitor them with a simple USB logic analyzer. Below is a screenshot of the USBEE logic analyzer. The bottom trace shows the GPIO lines being toggled to indicate when I enter and leave a certain section of code. It is a very accurate and simple way to make precise measurements.

Thanks mikeh....

All:

Where can I find definitions for configInfo.PLLCNTL1,  .PLLCNTL2, etc.?

It does not appear that PLLCNTL1 has the same bit mapping as CGCR1 (section 1.4.4.1 of SPRUFP0c), especially MH?

I have code that works,  but I would like to know why it works...

Hello,

I try with no success to get 150MHz with an external 12MHz.

I don't find why, and even if I used your configuration values, it doesn't work.

When I power down the PLL, I get well the 12MHz, but when I power on the PLL, with any configuration, the SYSCLK_OUT peak is under 2V and the fequency is 179MHz.

It seems to work not properly.

Can I have some help on mly problem ?

In your configuration values, why some bit are set otherwise they are reserved (in PLL_CNTL2 and PLL_CNTL1) ?

Thanks.

Diane

Hi,

The CLOCK_OUT pin cannot provide full voltage range swing clock over 100MHz. 

Regards,

Hyun

Hi,

Thanks for your reply.

When I use your configuration for 120MHz or 150MHz. The frequency measured in CLOCK_OUT is the same and is almost 179MHz.

Is it supposed to act this way ?

Thanks and Regards,

Diane

Hi,

How about other frequency 100MHz? Just for checking for something right. Normally you should see almost correct frequency. Did you provide 1.4V at 150MHz on CVDD and PLL power supply?

Regards,

Hyun

Hi,

For 100 MHz, I have the same problem: the SYSCLK_OUT peak is under 2V and the fequency is 179MHz.

If I power down the PLL, I get the 12 MHz. So I think that my external oscillator12 Mhz works properly, but I don't understand why I don't success to use the PLL with the 12 MHz.

Here on below the configuration I have used:

For 100MHz,

PLL_CNTL1 = 0x03E4;
PLL_CNTL2 = 0x0074;
PLL_CNTL3 = 0x0806;
PLL_CNTL4 = 0x0000;

For 120MHz,

PLL_CNTL1 = 0x03E4;
PLL_CNTL2 = 0x0060;
PLL_CNTL3 = 0x0806;
PLL_CNTL4 = 0x0000;

And for 150MHz,

PLL_CNTL1 = 0x03E4;
PLL_CNTL2 = 0x004C;
PLL_CNTL3 = 0x0806;
PLL_CNTL4 = 0x0000;

Even with your configuration, I get the same result.

I provide 1.4V for CVDD and VDDA_PLL.

With the 32.768KHz (when the CLK_SEL=0), I have no problem to get 100MHz or 120MHz, but it is limited to 120MHz and I whish to get 150MHz.

Thanks for your help.

Diane

Diane,

A couple of thoughts:

1. I believe that only the C5505 can be operated up to 150MHz. Are you using a C5515 chip?

2. If you are using the C5505 and want to operate at 150MHz, you must use the -15 variant. Take a look at this thread - http://e2e.ti.com/support/dsp/tms320c5000_power-efficient_dsps/f/110/t/182531.aspx

3. Are you waiting for the PLL control register to stabilize after changing its value? My code (which came from TI demo code) includes the below code after changing the control registers.

while ( (PLL_CNTL3 & 0x0008) == 0);

I hope this helps.

Hello MikeH,

Thanks a lot. You bring me some response.

To answer you:

1. It's ok, I use the C5505.

2. I get the -12 variant sample to test the C5505 and I power it at 1.4V. I didn't know that it could depend of C5505 partnumber. Where can I fin information about different partnumbers ?

3. I use the CSl library and it seems that the program waits for the stabilization (within the PLL_getTestLockMonStatus() function)

Diane