Connect C5509a with codec AIC23 over CPLD xc95144xl

Hi,

 Could you confirm on your CPLD IO configuration. If this is not correctly taken care, then issues that you are observing could occur.

 Let us know.

Regards

 Vasanth.

Thank Vasanth,

Thank you for your kind help

I have just found my cause of problem. That is I can not simply connect I2C pins from DSP to AIC23 over CPLD. I realized there were some discussion on the Internet on the same issues,

By the way, I would like to ask you another question regarding AIC23 working mode.
In short, I have a system with a DSP C5509a and two AIC23 connected to McBSP0 and McBSP1 over CPLD respectively.
The I2C pins of DSP are connected directly to both I2C of the two ACI23. I use one GPIO wired to pins Chip select (CS) of the two AIC23 which let me control the configuration process for each AIC23.
I wish to set the first AIC23 in master mode, and the second AIC23 in slave mode in which all the signal source (clocks, framsyns) provided by the first AIC23 through CPLD.
Does this system work?

Here are the configurations for the fisrt and second AIC23. My system mimicked the DSK c5509
AIC23_Params config1= {
0x0017, // 0 DSK5509_AIC23_LEFTINVOL Left line input channel volume
0x0017, // 1 DSK5509_AIC23_RIGHTINVOL Right line input channel volume
//0 dB
0x00F9, // 2 DSK5509_AIC23_LEFTHPVOL Left channel headphone volume
0x00F9, // 3 DSK5509_AIC23_RIGHTHPVOL Right channel headphone volume
//Line-input
//0x0010, // 4 DSK5509_AIC23_ANAPATH Analog audio path control
//mic input
0x0014,
0x0000, // 5 DSK5509_AIC23_DIGPATH Digital audio path control

0x0000, // 6 DSK5509_AIC23_POWERDOWN Power down control
0x0043, // 7 DSK5509_AIC23_DIGIF Digital audio interface format, AIC23 in master mode
0x000D, // 8 DSK5509_AIC23_SAMPLERATE Sample rate control 0x000D for 8 kHz ADC and DAC sample rate **MB
0x0001 // 9 DSK5509_AIC23_DIGACT Digital interface activation
};

AIC23_Params config2= {
0x0017, // 0 DSK5509_AIC23_LEFTINVOL Left line input channel volume
0x0017, // 1 DSK5509_AIC23_RIGHTINVOL Right line input channel volume
//0 dB
0x00F9, // 2 DSK5509_AIC23_LEFTHPVOL Left channel headphone volume
0x00F9, // 3 DSK5509_AIC23_RIGHTHPVOL Right channel headphone volume
//Line-input
//0x0010, // 4 DSK5509_AIC23_ANAPATH Analog audio path control
//mic input
0x0014,
0x0000, // 5 DSK5509_AIC23_DIGPATH Digital audio path control

0x0000, // 6 DSK5509_AIC23_POWERDOWN Power down control
0x0003, // 7 DSK5509_AIC23_DIGIF Digital audio interface format, AIC in slave mode
0x000D, // 8 DSK5509_AIC23_SAMPLERATE Sample rate control 0x000D for 8 kHz ADC and DAC sample rate **MB
0x0001 // 9 DSK5509_AIC23_DIGACT Digital interface activation
};

I am looking forward to hearing from you soon,

With best regards,

Hi,

You are correct that that CPLD does not support the open drain protocol of I2C, so I2C should connect directly from C5509A to both codecs.

The Chip select (CS) pin of the AIC23 when used in 2-wire (I2C) mode, simply determines seventh bit in the I2C device address. Most of the time CS should just be pull-ed high or low - not necessary to connect CS to a GPIO. With one AIC23 CS high and the other AIC23 CS low, you can write to 2 different I2C addresses to independently configure one as master and the other as slave.

CS: Control port input latch/address select. For SPI control mode this input acts as the data latch control. For
2-wire control mode this input defines the seventh bit in the device address field. See Section 3.1 for
details.

Keep in mind that the AIC23 is Not Recommended for New Designs (NRND) and that some codecs do not have this I2C address pin (CS), so they will be on the same I2C address (AIC3204 for example). In this case, you can use a mux to select which codec the I2C bus goes to. Like SN74CB3Q3253.

Hope this helps,
Mark

Dear Mark,

Thank you for your advice. I have followed it for my system, one codec wired to ground and the other wired to the Vdd with a resistor 10K (without this resistor the codec did not work). The I2C addresses of these two codecs are  0x1A and 0x1B respectively.

When I configured the both codecs working in master mode, every thing were fine;

However, when I configured one codec in master mode (address 0x1A), the another in the slave mode (I2C address 0x1B) of which pins BCLK, LRCIN, LRCOUT were sourced from the master codec over CPLD. Pin McLK of both codecs were connected to an oscillator 12 Mhz (followed the DSK C5509AIC). The I2C configurations were as in my previous post, they were different one another only in bit master mode or slave mode (bit MS) in register Digital Audio Interface Format (Address: 0000111). The system did not work - It appeared that the slave code was setup not as desired.

Could you please help me to resolve this problem?

I would like to thank you very much in advance,

With best regards,