according to OMAP5912 TRM, I can execute idle instruction on C55x side, and the program stall on there, but the IDLE_DSP bit in ARM_SYSST register never get asserted. hope there is someone still support OMAP5912 like me, we can have detail discussion.
TRM Page 193:
4.3.2 DSP Idle Control
The DSP idle instruction must be executed in host-only mode (HOM) to initiate the DSP idle mode. Depending on the settings of the DSP idle control registers (DSP_IDLECT1 and DSP_IDLECT2), different parts of the DSP subsystem go to idle mode when the IDLE instruction is executed.
The following procedure describes how the DSP enters idle mode:
1) Disable the watchdog timer.
When the timer/watchdog timer is configured as a watchdog, its clock (CK_REF/14) is never shut down.
2) Disable the following DSP peripheral clocks by setting the corresponding bits in DSP_IDLECT2 register to 0s.
_ DSP external peripheral clock
_ External reference peripheral clock
This disables the clocks immediately, regardless of whether the DSP clock is enabled or not. Or set the DSP_IDLECT1 corresponding bits to 1s, which disables the DSP peripheral clocks only when the DSP clock is disabled.
3) Switch the DSP TIPB and MPUI to shared access mode (SAM).
4) Program the DSP idle control register to put all the DSP subsystem domains in idle mode.
5) Switch the DSP TIPB and MPUI to host-only mode.
6) Execute the IDLE instruction.
7) When IDLE_DSP = 1 in ARM_SYSST register, the DSP_CK stops.
TRM Page 616:
2) DSP active to inactive state transition
a) DSP power domain is in active state.
b) Either the MPU requests the DSP to enter idle mode for inactive state via mailbox or shared memory, or the DSP OS enters the IDLE process.
c) The DSP programs the ICR register of the DSP to shut down all megacell subdomain clocks.
d) The DSP programs registers DSP_IDLECT1 and/or DSP_IDLECT2 of the OMAP3.2 CLKRST module to set the state of the OMAP3.2 DSP clock subdomains (CLKM2) (these belong to the MPU power domain and must be requested by the MPU).
e) The DSP masks/unmasks interrupts in the DSP interrupt handler to ensure a wake-up path.
f) The DSP executes the IDLE instruction.
g) The DSP input clock (DSP_CK) is shut down automatically by the OMAP CLKRST module.
h) The DSP power domain is in inactive state. The MPU can detect when the transition is completed by monitoring the IDLE_DSP bit in the ARM_SYSST register of the OMAP3.2 CLKRST module.
