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CCS/CCSTUDIO: I2C NACK handle

Stefano Carlesi
Expert 1325 points
Part Number: CCSTUDIO

Tool/software: Code Composer Studio

I'm using CSL I2C write and read functions, according to the "CSL_I2C_PollExample". C5517 device.

I notice that when a NACK occur the SCL is held low. I'm testing it with no slave devices on the I2C bus, DSP as I2C Master.

According to the manual user should:

6.2.9.2 User Response to a NACK
The user must perform the following steps when responding to a NACK.
1. Set ICMDR.STP, which sends a STOP bit and releases SCL.
2. Set ICSTR.NACK=1 to clear the flag.
3. Wait for ICMDR.MST to self-clear before initiating further I2C transactions.
When the MST bit clears, the controller has finished sending the STOP bit. Verify the MST bit clears by
checking if ICMDR.MST is equal to 0 at the start of the function. This check allows the processor time
to perform other tasks but not start a new transaction until ICMDR.MST has cleared.

Does not CSL function handle the NACK event? Do I have to add code handling the NACK event as specified on the manual?

Thank you

Stefano

  • 0
    TI__Guru**** 161600 points
    Hi Stefano,

    Could you share exactly which SDK are you using? Which version of the I2C driver?

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 1325 points

    Hi Yordan,

    I'm using c55_csl_3.04 with CCS5.


    /** @file csl_i2c.c
    *
    * @brief I2C functional layer API source file
    *
    * Path: \(CSLPATH)\ src
    */

    /* ============================================================================
    * Revision History
    * ================
    * 08-Oct-2008 Created
    * 23-Oct-2008 Updated for code review comments
    * 13-Aug-2010 CSL v2.10 release
    * 06-Jul-2011 CSL v2.50 release
    * 13-Sep-2012 CSL v3.00 release
    * 20-Dec-2012 CSL v3.01 release
    * ============================================================================
    */

  • 0 in reply to Stefano Carlesi
    TI__Guru**** 161600 points
    Ok, I've notified the RTOS team.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 1325 points

    Also, I notice from the I2C_write CSL function that no STOP condition is sent after the data has been sent.

    How should start and stop conditions has to be handled on a I2C polling mode using I2C_write CSL functions? I don't see a stop condition on the CSL_I2C_PollExample_Out.

    I need to use I2C master-transmitter mode. On my application I need to  outputs to a I2C Io expander.

    csl_i2c_ioExpander.c also didn't help my issue.

  • 0 in reply to Stefano Carlesi
    TI__Mastermind 30365 points

    Stefano,

    There seems to be a startstop command in read and write I2C data in csl_i2c_polled_example.c

    status = I2C_read(gI2cRdBuf, CSL_I2C_DATA_SIZE, CSL_I2C_EEPROM_ADDR,

                 gI2cWrBuf, CSL_EEPROM_ADDR_SIZE, TRUE,

                 startStop, CSL_I2C_MAX_TIMEOUT, FALSE);

    Is that what you are referring to as missing?

    Lali

  • 0 in reply to Lalindra Jayatilleke
    Expert 1325 points

    Hello Lali,

    thank you for your reply.

    I noticed that the CSL function does handle START and STOP but looking at the code in csl_i2c.c file it seems to me that it asserts the start and stop bit on the ICMDR register. Reading the C5517 reference manual I understand that the stop bit is sent once the data I2C data couter is 0 (all data is transmitted).

    My question is: what happen if a timeout or a NACK occur? How should I handle a timeout/NACK condition? I tested this and I saw with the oscilloscope that once a NACK or timeout occur the SCL in held low and the Busy Bit = 1 (that is because the STOP condition has not been sent!). 

    I need to use a I2C polling mode.

    Thank you,

    Stefano

  • 0 in reply to Stefano Carlesi
    Expert 1325 points

    Still waiting for a kind answer.

    Could you please let me know?

    Thank you