CCS/TMS320VC5510A: MCBSP SERIAL PORT

SANDHYA PRAJAPATI

Part Number: TMS320VC5510A

Tool/software: Code Composer Studio

The goal is to implement SPI with 50MHz serial clock and 16 bit word length using McBSP ports in c5510 dsk kit. And analyse the clock on DSO(digital storage oscilloscope)

implementing SPI interface using McBSP port of c5510 dsk kit in CCS V2 for C5510 DSK. configured McBSP using DSP BIOS with serial clock 25MHz and word width 16 bit. want to analyze transmitter clock output on CLKX0 pin no. 21 on peripheral expansion connector on DSK board using probe on DSO( with sampling bandwidth in GHz). Build the C code in CCS , it bult without any errors. load program and run it. on seeing the McBSP registers value in editor window find the final 16 bit data value got updated in DXR0 register. But not getting any signal and clock on digital storage oscilloscope, not even any fluctuations.

Also, when probing pin no. 78 of P2 connector, which gives CLKOUT some saw tooth kind of waveform with time period of near about 10ns amplitude less than 1V. and CLKMD register which is used to configure the div and mul bits of pll to get desired clock output, shows value o 2CD3 (it can be seen in view tool --> peripheral register), according to which the pll is dividing the main clock input by 3 and multipyling it by 25. calculating the value it should give at CLKOUT is also not matching with what is being seen on DSO.

over 6 years ago

0 Cvetolin Shulev-XID over 6 years ago

TI__Guru 65405 points

Hi Sandhya,

Could you share your C code and register values?

BR
Tsvetolin Shulev

0 SANDHYA PRAJAPATI over 6 years ago in reply to Cvetolin Shulev-XID

Prodigy 80 points

Hi Tsvetolin,

following is the C code that am running followed by the configuration file that contain the register values. The configuration file is automatically generated as i have used DSP BIOS configuration.

////////////////////////////////////////////////////////////////////////////////// C code //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

#include <std.h>

#include <log.h>

/*need to include this genenrated file while using DSP/BIOS */

#include "mc_txcfg.h"

#include <csl_irq.h>

#define N 10

/* This example places the MCBSP in CLOCK STOP MODE to perform a simple 16 bit single-frame mode transfer.*/

/* The example uses predefined CSL macros and symbolic */

/* constants to create the initialization values needed for */

/* the MCBSP control registers. */

/* In this example we have used the DSPBIOS/CSL GUI */

/* configuration tool to statically define all MCBSP_Handle */

/* and MCBSP_Config objects that will be used to initialize */

/* the MCBSP registers for the given transfer. */

/* The DSPBIOS/CSL configuration tool generates two C files */

/* mcbspcfg.h and mcbspcfg_c.c. The C header file, mcbspcfg.h */

/* contains the extern declarations for all MCBSP_Config and */

/* MCBSP_Handle objects that were creatred as a result of CSL */

/* GUI options that were selected. The C source file, */

/* mcbspcfg_c.c contains the definitions of these objects and */

/* their initialization values. In addition, the C source */

/* file defines a function, CSL_cfgInit that contains calls */

/* the the MCBSP_open and MCBSP_config functions to pre-open */

/* and pre-configure the MCBSP channel for us. */

Uint16 xmt[N],xmt1[N],xmt2[N];

volatile Uint16 Xfrcnt = 0;

Uint16 err = 0;

Uint16 old_intm;

Uint16 xmtEventId, xmtEventId1,xmtEventId2;

void taskFxn(void);

void main(void)

{

Uint16 i;

for (i = 0; i <= (N - 1); i++) {

xmt[i] = ((Uint16)i << 9) + i;

;

}

for (i = 0; i <= (N - 1); i++) {

xmt1[i] = ((Uint16)i << 7) + i;

;

}

for (i = 0; i <= (N - 1); i++) {

xmt2[i] = ((Uint16)i << 5) + i;

;

}

taskFxn(); /*calling task function */

}

void taskFxn(void)

{

Uint16 i;

/*Temporarily disable all maskable interrupts */

old_intm = IRQ_globalDisable();

/* Get Event Id's associated with MCBSP 0 receive and transmit */

/* The MCBSP_Handle object, hMcbsp0 has been predefined */

/* in the code automatically generated by the DSPBIOS/CCSL */

/* GUI config */

/*rcvEventId = MCBSP_getRcvEventId(hMcbsp0);*/

xmtEventId = MCBSP_getXmtEventId(hMcbsp0);

xmtEventId1 = MCBSP_getXmtEventId(hMcbsp1);

xmtEventId2 = MCBSP_getXmtEventId(hMcbsp2);

/* Clear any pending receive/transmit interrupts */

/*IRQ_clear(rcvEventId);*/

IRQ_clear(xmtEventId);

IRQ_clear(xmtEventId1);

IRQ_clear(xmtEventId2);

/* Enable receive/transmit interrupts */

/*IRQ_enable(rcvEventId); */

IRQ_enable(xmtEventId);

IRQ_enable(xmtEventId1);

IRQ_enable(xmtEventId2);

/* Start Sample Rate Generator and enable Frame Sync */

MCBSP_start(hMcbsp0,

MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,

0x3000);

/* Take MCBSP transmit and receive out of reset */

MCBSP_start(hMcbsp0,

MCBSP_XMIT_START ,

0x3000);

MCBSP_start(hMcbsp1,

MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,

0x3000);

/* Take MCBSP transmit and receive out of reset */

MCBSP_start(hMcbsp1,

MCBSP_XMIT_START ,

0x3000);

MCBSP_start(hMcbsp2,

MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,

0x3000);

/* Take MCBSP transmit and receive out of reset */

MCBSP_start(hMcbsp2,

MCBSP_XMIT_START ,

0x3000);

/* Prime MCBSP DXR */

while(!MCBSP_xrdy(hMcbsp0)) {

;

}

MCBSP_write16(hMcbsp0,xmt[0]);

while(!MCBSP_xrdy(hMcbsp1)) {

;

}

MCBSP_write16(hMcbsp1,xmt1[0]);

while(!MCBSP_xrdy(hMcbsp2)) {

;

}

MCBSP_write16(hMcbsp2,xmt2[0]);

/* Begin data transfer loop. We will loop thru to transmit */

/* and receive the data.

for (i=1; i<=(N-1);i++) {

/* Wait for XRDY signal before writing data to DXR */

while (!MCBSP_xrdy(hMcbsp0)){;}

/* Write 16 bit data value to DXR */

IRQ_disable(xmtEventId);

MCBSP_write16(hMcbsp0,xmt[i]);

if (i == 10) {

IRQ_disable(xmtEventId);

MCBSP_reset(hMcbsp0);

}

else {

IRQ_enable(xmtEventId);

}

/* Wait for XRDY signal before writing data to DXR */

while (!MCBSP_xrdy(hMcbsp1)){;}

/* Write 16 bit data value to DXR */

IRQ_disable(xmtEventId1);

MCBSP_write16(hMcbsp1,xmt1[i]);

if (i == 10) {

IRQ_disable(xmtEventId1);

MCBSP_reset(hMcbsp1);

}

else {

IRQ_enable(xmtEventId1);

}

/* Wait for XRDY signal before writing data to DXR */

while (!MCBSP_xrdy(hMcbsp2)){;}

/* Write 16 bit data value to DXR */

IRQ_disable(xmtEventId2);

MCBSP_write16(hMcbsp2,xmt2[i]);

if (i == 10) {

IRQ_disable(xmtEventId2);

MCBSP_reset(hMcbsp2);

}

else {

IRQ_enable(xmtEventId2);

}

/* Enable all maskable interrupts */

IRQ_globalRestore(old_intm);

MCBSP_close(hMcbsp0);

MCBSP_close(hMcbsp1);

MCBSP_close(hMcbsp2);

}

/////////////////////////////////////////////////////////////////////////////////////////////////////////// Configuration file /////////////////////////////////////////////////////////////////////////////

/* Do *not* directly modify this file. It was */
/* generated by the Configuration Tool; any */
/* changes risk being overwritten. */

/* INPUT mc_tx.cdb */

/* Include Header File */
#include "mc_txcfg.h"

#pragma CODE_SECTION(CSL_cfgInit,".text:CSL_cfgInit")

/* Config Structures */
EMIF_Config emifCfg0 = {
0x0221, /* Global Control Register */
0xffff, /* Global Reset Register */
0x3fff, /* CE0 Space Control Register 1 */
0x5fff, /* CE0 Space Control Register 2 */
0x0000, /* CE0 Space Control Register 3 */
0x1038, /* CE1 Space Control Register 1 */
0x0038, /* CE1 Space Control Register 2 */
0x0000, /* CE1 Space Control Register 3 */
0x1050, /* CE2 Space Control Register 1 */
0x0050, /* CE2 Space Control Register 2 */
0x0000, /* CE2 Space Control Register 3 */
0x1050, /* CE3 Space Control Register 1 */
0x0050, /* CE3 Space Control Register 2 */
0x0000, /* CE3 Space Control Register 3 */
0x2b11, /* SDRAM Control Register 1 */
0x0578, /* SDRAM Period Register */
0xffff, /* SDRAM Initialization Register */
0x0535 /* SDRAM Control Register 2 */
};

MCBSP_Config mcbspCfg0 = {
0x1880, /* Serial Port Control Register 1 */
0x0010, /* Serial Port Control Register 2 */
0x0000, /* Receive Control Register 1 */
0x0000, /* Receive Control Register 2 */
0x0040, /* Transmit Control Register 1 */
0x0005, /* Transmit Control Register 2 */
0x0006, /* Sample Rate Generator Register 1 */
0x300e, /* Sample Rate Generator Register 2 */
0x0000, /* Multichannel Control Register 1 */
0x0200, /* Multichannel Control Register 2 */
0x0e08, /* Pin Control Register */
0x0000, /* Receive Channel Enable Register Partition A */
0x0000, /* Receive Channel Enable Register Partition B */
0x0000, /* Receive Channel Enable Register Partition C */
0x0000, /* Receive Channel Enable Register Partition D */
0x0000, /* Receive Channel Enable Register Partition E */
0x0000, /* Receive Channel Enable Register Partition F */
0x0000, /* Receive Channel Enable Register Partition G */
0x0000, /* Receive Channel Enable Register Partition H */
0x1111, /* Transmit Channel Enable Register Partition A */
0x0000, /* Transmit Channel Enable Register Partition B */
0x0000, /* Transmit Channel Enable Register Partition C */
0x0000, /* Transmit Channel Enable Register Partition D */
0x0000, /* Transmit Channel Enable Register Partition E */
0x0000, /* Transmit Channel Enable Register Partition F */
0x0000, /* Transmit Channel Enable Register Partition G */
0x0000 /* Transmit Channel Enable Register Partition H */
};

MCBSP_Config mcbspCfg1 = {
0x1880, /* Serial Port Control Register 1 */
0x0010, /* Serial Port Control Register 2 */
0x0000, /* Receive Control Register 1 */
0x0000, /* Receive Control Register 2 */
0x0040, /* Transmit Control Register 1 */
0x0005, /* Transmit Control Register 2 */
0x0006, /* Sample Rate Generator Register 1 */
0x300e, /* Sample Rate Generator Register 2 */
0x0000, /* Multichannel Control Register 1 */
0x0200, /* Multichannel Control Register 2 */
0x0e08, /* Pin Control Register */
0x0000, /* Receive Channel Enable Register Partition A */
0x0000, /* Receive Channel Enable Register Partition B */
0x0000, /* Receive Channel Enable Register Partition C */
0x0000, /* Receive Channel Enable Register Partition D */
0x0000, /* Receive Channel Enable Register Partition E */
0x0000, /* Receive Channel Enable Register Partition F */
0x0000, /* Receive Channel Enable Register Partition G */
0x0000, /* Receive Channel Enable Register Partition H */
0x1111, /* Transmit Channel Enable Register Partition A */
0x0000, /* Transmit Channel Enable Register Partition B */
0x0000, /* Transmit Channel Enable Register Partition C */
0x0000, /* Transmit Channel Enable Register Partition D */
0x0000, /* Transmit Channel Enable Register Partition E */
0x0000, /* Transmit Channel Enable Register Partition F */
0x0000, /* Transmit Channel Enable Register Partition G */
0x0000 /* Transmit Channel Enable Register Partition H */
};

MCBSP_Config mcbspCfg2 = {
0x1880, /* Serial Port Control Register 1 */
0x0010, /* Serial Port Control Register 2 */
0x0000, /* Receive Control Register 1 */
0x0000, /* Receive Control Register 2 */
0x0040, /* Transmit Control Register 1 */
0x0005, /* Transmit Control Register 2 */
0x0006, /* Sample Rate Generator Register 1 */
0x300e, /* Sample Rate Generator Register 2 */
0x0000, /* Multichannel Control Register 1 */
0x0200, /* Multichannel Control Register 2 */
0x0e08, /* Pin Control Register */
0x0000, /* Receive Channel Enable Register Partition A */
0x0000, /* Receive Channel Enable Register Partition B */
0x0000, /* Receive Channel Enable Register Partition C */
0x0000, /* Receive Channel Enable Register Partition D */
0x0000, /* Receive Channel Enable Register Partition E */
0x0000, /* Receive Channel Enable Register Partition F */
0x0000, /* Receive Channel Enable Register Partition G */
0x0000, /* Receive Channel Enable Register Partition H */
0x1111, /* Transmit Channel Enable Register Partition A */
0x0000, /* Transmit Channel Enable Register Partition B */
0x0000, /* Transmit Channel Enable Register Partition C */
0x0000, /* Transmit Channel Enable Register Partition D */
0x0000, /* Transmit Channel Enable Register Partition E */
0x0000, /* Transmit Channel Enable Register Partition F */
0x0000, /* Transmit Channel Enable Register Partition G */
0x0000 /* Transmit Channel Enable Register Partition H */
};

/* Handles */
MCBSP_Handle hMcbsp0;
MCBSP_Handle hMcbsp1;
MCBSP_Handle hMcbsp2;

/*
* ======== CSL_cfgInit() ========
*/
void CSL_cfgInit()
{
hMcbsp0 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
hMcbsp1 = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
hMcbsp2 = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET);

EMIF_config(&emifCfg0);
MCBSP_config(hMcbsp0, &mcbspCfg0);
MCBSP_config(hMcbsp1, &mcbspCfg1);
MCBSP_config(hMcbsp2, &mcbspCfg2);

/* You must use DMA_start() in your main code to start the DMA. */

/* You must use MCBSP_start() in your main code to start the MCBSP. */

}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

0 Lalindra Jayatilleke over 6 years ago

TI__Mastermind 30365 points

Sandhya,

Not sure what might be going on in your setup.
What software base are you using? is it the C55x CSL?

Also, you may want to take a look at this thread where there's some C5510 example code posted by someone using the McBSP in SPI mode.

Lali

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CCS/TMS320VC5510A: MCBSP SERIAL PORT