How to use EDMA for SRIO transfer on c6455/6474

SNBANIK

I have been running SRIO CSL examples on c6455 EVM - transferring data from one DSP to the other. The example uses programmed transfer using NWRITE (that is the DSP CPU writes to the SRIO LSU register 5 to cause the transfer). My need is to transfer big chunks (say a frame size of 256KBytes) continously and it would be a huge overhead on DSP CPU cycles if the DSP CPU has to send it 4K at a time. My objective is to use EDMA to do the transfer and interrupt the DSP core at the end of transfer of one full frame.

Can someone point me to any example code or provide help on how to do it (EDMA setup etc). The list of EDMA3 channel events (Table 2.6 in SPRU966a) doesn't include any SRIO events.

Currently I am prototyping using c6455 but I would be need to do the same for 6474 too.

Thanks,

Somnath Banik

over 16 years ago

0 RandyP over 16 years ago

TI__Guru* 84110 points

Although I do not have a sample code that I can offer to you, I do know that people have implemented exactly what you want to do.

On the C6455, EDMA3 channel 20 is associated with INTDST1 which is the SRIO Interrupt 1.

The procedure you would follow is

Configure you SRIO transfers to send INTDST1 when each transfer is completed and needs new programming.
Build a table of the LSU register values that need to be written for each sequential transfer. If there are 6 registers to write and 64 sets of 4KB, the table will be 6x64=384 words in length.
Program DMA channel 20 with ACNT=24 (bytes), BCNT=64 (SRIO operations to do), ASYNC, TCINTEN=1.
Manually trigger the first transfer once you are ready, then when each transfer completes INTDST1 will trigger the next transfer.
When the last transfer has started (DMA 20 completed), the DSP will get an interrupt.

If you want to get the DSP interrupt after the last SRIO transfer has completed rather than when it starts, set TCINTEN=0 and instead program that last transfer set of LSU register values so that it will generate a different event, like INTDST0, and enable INTDST0 to the DSP.

You may need to be careful with handling any error conditions that might occur. The PHY level will take care of a lot of the errors, but you may need to enable the DSP to take corrective action in some cases.

0 SNBANIK over 16 years ago in reply to RandyP

Intellectual 645 points

Randy

Thanks for your suggestions. I had somehow missed the SRIO INT event.

As per your suggestions, I did a quick prototype with the exception that I am only writing LSU_REG5 using EDMA (for the quick prorotype). Hence the ACNT is 4 (Bytes). I setup rest of the registers using programmed write. My objective is to first get one line transferred using EDMA and SRIO.

I used one of the EDMA CSL example code to prototype this (edma_interrupt_example.c).

I use the EDMA to write to LSU register address 0x02d00414 and used manual trigger.

Unfortunately the SRIO transfer is not happening.

Any clue as to what I may be missing?

-- Somnath

0 RandyP over 16 years ago in reply to SNBANIK

TI__Guru* 84110 points

Please take a look at an example project I posted on another thread: http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/11561/45088.aspx#45088 [edit: RandyP to correct the link] .

I have verified this example on a DSK6455. It will likely need some minor modifications for the C6474 for the different interrupt and event combiners, but the basic concept will remain.

Your plan above is perfect. I will hope that merging this new example code into your project (or the other way around) will end in success. Please let us know, either way.

0 RandyP over 16 years ago in reply to RandyP

TI__Guru* 84110 points

An update was required to one of the files in my example code. If you have downloaded that example, please go to http://e2e.ti.com/forums/p/9057/40242.aspx#40242 to see the update text, and then download the zip file again since it now has the updated file.

0 SNBANIK over 16 years ago in reply to RandyP

Intellectual 645 points

My immediate issue is as follows --

While I can get memory to memory transfer done using EDMA with manual trigger, I am unable to get the same going for memory to SRIO registers write using manual trigger.

I setup the EDMA to write to LSU0_REG5 (write to LSUn_REG5 trigegrs the SRIO transfer) but the register never gets written. EDMA transfer trigger is manual.

If I do the same using prorgarrmed write (CPU writing to the LSU register), then it is successful.

Can you provide some clue as to what could be the reason?

Thanks,

SBanik

0 RandyP over 16 years ago in reply to SNBANIK

TI__Guru* 84110 points

The version of the datasheet that I have is SPRS276I. At the top of page 80 is Table 4-1 "SCR Connection Matrix" which shows the connections that are available (and are not available) from every internal bus master to every internal bus slave.

The SRIO registers are on the ConfigBus which requires the bus master to access the Configuration SCR. In this table, you will see that only one of the four Transfer Controllers can access the Config SCR.

If you are using CSL for your EDMA access, then you can set the Queue number for each DMA and QDMA channel at the CSL_edma3HwSetup step. If you are using the standard examples, then your code could look like this:

dmahwSetup[nChNum].que = CSL_EDMA3_QUE_1;
hwSetup.dmaChaSetup = dmahwSetup;
hwSetup.qdmaChaSetup = qdmahwSetup;
status = CSL_edma3HwSetup(hModule,&hwSetup);

0 SNBANIK over 16 years ago in reply to RandyP

Intellectual 645 points

Randy,

With this suggestion I am able to get one more step but now the DSP CPU is forever in Inernal ROM.

Here is the code snippet.

----------------------------------------------------------------------------------

lsu_no = SELECTED_LSU ; /* value of SELECTED_LSU is 1 */

lsu_setup_status = SonoCSL_srioLsuSetup (hSrio, &lsu_conf, lsu_no);    /* This is same function as TI CSL with a modifcation - write to LSUn_REG5 is commented out */
lsu_reg5_Val =
                CSL_FMK(SRIO_LSU_REG5_DRBLL_INFO, lsu_conf.doorbellInfo)|
                CSL_FMK(SRIO_LSU_REG5_HOP_COUNT, lsu_conf.hopCount)|
                CSL_FMK(SRIO_LSU_REG5_PACKET_TYPE, lsu_conf.pktType);

GetParamHandle(0) ;
Setup_EdmaTxParams((void *)&lsu_reg5_Val, (void *)0x02d00414, 4) ; /* write to LSU1_REG5 using EDMA */
intFlag = 0 ;
edma_trigger_transfer();

    /* Wait for the completion of transfer */
    response.index = lsu_no;
    do {
        CSL_srioGetHwStatus (hSrio, CSL_SRIO_QUERY_LSU_BSY_STAT, &response);
    }while(response.data == 1);

--------------------------------------------------------------------------

What happens is after the edma_trigger_transfer() is executed, I find that the SRIO LUS1_REG5 gets written but the DSP CPU is now always in Internal ROM (address range 0x0010 0000 - 0x0010 7FFF).

0 RandyP over 16 years ago in reply to SNBANIK

TI__Guru* 84110 points

SNBANIK said:

GetParamHandle(0) ;
Setup_EdmaTxParams((void *)&lsu_reg5_Val, (void *)0x02d00414, 4) ; /* write to LSU1_REG5 using EDMA */
edma_trigger_transfer();

I am not familiar with any of these functions. They do not appear anywhere on my PC when I do a full search, and I have both CSL and LLD installed. I can only say that something is wrong. The easiest guess is an interrupt is occurring that is not initialized properly.

Other than that, I can only suggest to single step in the edma_trigger_transfer function to get to a point where the failure is occurring.

0 SNBANIK over 16 years ago in reply to RandyP

Intellectual 645 points

Randy,

I am sorry. I should have inlcuded those functions. I created those temporary functions for quick prototype.

I have some globals declared as

CSL_Edma3ParamHandle hParamBasic;

CSL_Edma3ParamSetup myParamSetup;

CSL_Edma3ChannelHandle hChannel;

void GetParamHandle(short paRamNum)
{

hParamBasic = CSL_edma3GetParamHandle(hChannel,paRamNum,&status);
    if (hParamBasic == NULL) {
        printf("Edma get param handle failed\n");
        return;
    }

}

void Setup_EdmaTxParams(void * psrcBuff, void * pdestBuff, unsigned short size)
{
    /* Edma parameter entry Setup */
    myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
                                             CSL_EDMA3_TCCH_DIS, \
                                             CSL_EDMA3_ITCINT_DIS, \
                                             CSL_EDMA3_TCINT_EN,\
                                             1,CSL_EDMA3_TCC_NORMAL,\
                                             CSL_EDMA3_FIFOWIDTH_NONE, \
                                             CSL_EDMA3_STATIC_DIS, \
                                             CSL_EDMA3_SYNC_A, \
                                             CSL_EDMA3_ADDRMODE_INCR, \
                                             CSL_EDMA3_ADDRMODE_INCR);
    myParamSetup.srcAddr = (Uint32)psrcBuff;
    myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(size,1);
    myParamSetup.dstAddr = (Uint32)pdestBuff;
    myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,0);
    myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (CSL_EDMA3_LINK_NULL,
                                                           1);
    myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);
    myParamSetup.cCnt = 1;
    status = CSL_edma3ParamSetup(hParamBasic,&myParamSetup);
    if (status != CSL_SOK) {
        printf ("Edma param setup failed\n");
        return;
    }

}

void edma_trigger_transfer(void)
{
    /* Manually trigger the channel */
    status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
    if (status != CSL_SOK) {
        printf ("Edma channel set command failed\n");
        return;
    }
}

0 RandyP over 16 years ago in reply to SNBANIK

TI__Guru* 84110 points

In Setup_EdmaTxParams, change CSL_EDMA3_TCINT_EN to CSL_EDMA3_TCINT_DIS to turn off the EDMA interrupt. If the DSP no longer ends up in ROM, then you have proof that it is the interrupt that is causing the problem.

If this is the case, you may want to take a look at an example project I posted on another thread, http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/11561/45088.aspx#45088 [edit RandyP to correct the link] . This example uses two manually triggered channels and handles separate interrupts for each.

If turning off the interrupt did not solve the problem, something else is causing the PC to get lost. But nothing in your code should do that. So you will have some debugging to do.

0 SNBANIK over 16 years ago in reply to RandyP

Intellectual 645 points

Thanks Randy.

It works now and the SRIO transfer is happening with manual triggered EDMA.

The question remains why the EDMA transfer complete interrupt enable is causing the problem. In my prototype code, I use the same call to setup memory to memory transfer with transfer complete interrupt enabled and it works. The ISR gets executed properly for the memory to memory transfers.

I will investigate that separately. If you have a plausible reason for such behavior, that would be great.

0 SNBANIK over 16 years ago in reply to RandyP

Intellectual 645 points

Randy,

I need some clarification on INTDST1.

Table 7-4 C6455 EDMA Channel Synchronization Table in SPRS276C mentions EDMA CHANNEL 20 as RIOINT1 event.

Again Table 7-7 (C6455 DSP Interrupts) in the same document mentions EVENT NUMBER 20 as RIOINT0, EVENT NUMBER 21 as RIOINT1 and EVENT NUMBER 22 as RIOINT4.

There seems to be discrepancy betrween the two and also you mentioned INTDST1. Is INTDST1 same as RIOINT1?

I am also trying to understand more about the differences between RIOINT0, RIOINT1 and RIOINT4. Is RIOINT0 associated with LSU0 and RIOINT1 with LSU1? If so, what is RIOINT4 associated with. I can't find reference to RIOINT anywhere else in the document.

When I look at spru976 (March 2006) -- SRIO User Guide - I don't find any reference at all to RIOINT0 or 1 or 4. This document has refernce to INTDST0 to INTDST7 as in INTDST0_DECODE, INTDST1_DECODE, INTDST0_RATE_CNTL etc

I am trying to understand the link between INTDSTn to RIOINTm as also the link with the INTERRUPT_REQ field in the LSUn_REG4 (spru976).

Any help would be greatly appreciated.

0 RandyP over 16 years ago in reply to SNBANIK

TI__Guru* 84110 points

The version of the datasheet that I have is SPRS276I. Please update your copy of the datasheet from www.ti.com, search for C6455 product folder, then look at these same sections to understand how the SRIO and EDMA and CPU interact. While you are in the C6455 product folder getting documentation, look for the latest versions for all the C6455 documents you have downloaded. The names may be more consistent when you get all of the latest versions.

0 Eddie3909 over 15 years ago in reply to RandyP

Guru 10385 points

Hi RandyP

I'd like to find the example project you posted in the above thread (copied link to below). Seems all the links are broken after the E2E community was updated a couple months back.

Please take a look at an example project I posted on another thread: http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/11561/45088.aspx#45088 [edit RandyP to correct the link].

I'm trying to do the same thing on a C6472 that Somnath tried on the C6455. The documentation seems to be missing how to tie the LSU event to the EDMA RIOINT event.

Thanks a bunch.

Cheers
Eddie

0 RandyP over 15 years ago in reply to Eddie3909

TI__Guru* 84110 points

Please look for this example project at http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/11561/45088.aspx#45088 . It runs on the C6455 and shows how to write the CSL and interrupt code to use EDMA3 for a couple of transfers.

It does not specifically have any relation to SRIO, though.

In the C6472 datasheet SPRS612A, find the EDMA3 Channel Synchronization Events table (Table 7-4 in SPRS612a) and find the four (4) RapidIO Events; note the labels INTDST4-7. These are the available events that will allow the SRIO to trigger the corresponding DMA channel. Then find the RapidIO Control Registers table (Table 7-150) and look for the LSU Interrupt Condition Routing Registers and note their labels, LSU_ICRR0-3. Next, go to the SRIO User's Guide SPRUE13H to find the description of the LSU_ICRR0-3 registers, Figure 56 on page 104; the bit field descriptions are actually on an earlier page, Table 41 on page 101. It will be good to read the whole of Chapter 4 Interrupt Conditions to get a complete understanding of how the SRIO interrupts work and how they are controlled through the registers.

As a simplification which leaves out a lot of other complex possibilities, here is a sequential list of the procedure to get an LSU interrupt to trigger a DMA channel:

There are four EDMA3 input events that you can choose from, INTDST7. Pick one for one of your LSUs and do not use this same one for any other interrupts. For this discussion, I will assume that you choose INTDST7 to be triggered by an interrupt from LSU1. I chose INTDST7 because it is the same as RIOINT7 which can be used by any of the six DSP cores.
Program LSU_ICRR0.ICR0=0111b to route LSU_ICSR.ICS0 [LSU1 Transaction complete, No errors (posted/non-posted)] to INTDST7 for LSU1. LSU_ICRR0.ICR0 tells it to route a completion interrupt (bit 0 of LSU_ICSR) from LSU1 (because it was bit 0 of LSU_ICSR) to INTDST7 (because of the value 0111b).
Program LSU1_REG4.INTERRUPT_REQ (bit 0) = 1 so LSU1 will generate an interrupt when the transaction is complete.
Program DMA channel 31 INTDST7 to write new values to LSU1_REG0-5 to trigger another DirectIO transaction.

I do not know if there is a requirement to also route this interrupt INTDST7 (also known as RIOINT7) to an interrupt in one of the cores so you can clear any interrupt condition. I do not expect that this is the case, but you will need to determine if that is the case or not or at least keep it in mind if you run into trouble. If you do need to route this to an interrupt also, you can either use the EDMA interrupt or the INTC interrupt from RIOINT7.

0 Eddie3909 over 15 years ago in reply to RandyP

Guru 10385 points

Hi Randy

Your comments really help to understand how the mapping of SRIO interrupts to EDMA events is done.

Also found the DIO Library helpful. It has C6455 and C6474 examples https://gforge.ti.com/gf/project/sriodirectiolib/

I looked at the C6455 C6472 and C6474 and it looks like RIOINT is synonymous with INTDST. True?

I also noticed there are SRIO interrupt pacing registers. Each register INTDSTx_RATE_CNTL is mapped to an INTDSTx. From what I've read, these should be set to zero so that the EDMA event occurs at the end of the requested transaction. True?

Thanks again

Cheers

0 Mugiwara over 15 years ago in reply to Eddie3909

Prodigy 70 points

HI ,

i loocked hard on ( table 2_6 on SPRUG11a), to find the channel on EDMA3 ,which is mapped to the Srio interupt , but i didnt found it .

there is no Srio event mapped to any channel .

i want it to initiate transfers using SRIO , with EDMA .

please help.

0 Abdessamad over 15 years ago in reply to Mugiwara

Prodigy 35 points

i forget to mention that im working on evm 6474

0 Dieter Landl over 15 years ago in reply to Abdessamad

Prodigy 60 points

First: RIOINTx means the same as INTDSTx

Please have a look at 'Table 14. Input Events to CIC3' in chapter '9 CIC Event Lists for TPCC' in 'SPRUFK6':

There the input events 21 .. 27 are bound to RIOINT0 .. 7 (6 is not available on C6474)

By means of CIC3 configuration you can route the input events to TPCC input events as shown in Table 2-6. of SPRUG11A referenced as CIC3_EVTx.

0 Dieter Landl over 15 years ago in reply to Eddie3909

Prodigy 60 points

High Eddie,

your are right with your assumption "RIOINT is synonymous with INTDST".

This was a pitfall for me too.

Greetings

Dieter

0 Mugiwara over 15 years ago in reply to Dieter Landl

Prodigy 70 points

Please can you give me ,an exemple code for using srio interrupt ,to isuue transfert >4Kbyte.

thanks.

Mugiwara

0 Dieter Landl over 15 years ago in reply to Mugiwara

Prodigy 60 points

Mugiwara said:

Hi

Please can you give me ,an exemple code for using srio interrupt ,to isuue transfert >4Kbyte.

thanks.

Mugiwara

Hello Mugiwara!

I would advice you to have a research of the postings before posting a question.

Have a look at the posting

"Posted by RandyP on 3 Feb 2010 9:14 PM " -->

"Please look for this example project at http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/11561/45088.aspx#45088 . It runs on the C6455 and shows how to write the CSL and interrupt code to use EDMA3 for a couple of transfers."

Greetings

Dieter

0 Eddie3909 over 15 years ago in reply to Dieter Landl

Guru 10385 points

Also search the Wiki. There is a DIO library available for SRIO. See this thread.

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/11391/145624.aspx#145624

[edit Moderator] And the DIO library Wiki topic is at http://www.tiexpressdsp.com/index.php/DIO_Library .

Cheers

Eddie

0 Abdessamad over 15 years ago in reply to RandyP

Prodigy 35 points

HI Landl
Im using evm 6474

I did the configuration to route the interuption of SRIO to RIOINT1 , then i used the cic3 to route RIOINT1 to CIC _EVT4,
i did the configuration to the option field of parametre setup as shown in the code. but it doesn't work.

    param.eventId = CSL_CIC3_EVENTID_RIOINT1;
    param.ectlEvtId = CSL_CIC_ECTL_EVT4;

    hCic = CSL_cicOpen(&cicObj, CSL_CIC_0, &param , &intStat);

    hSrio = (CSL_SrioHandle) Srio_Init();

    hSrio->regs->LSU_ICSR = 0x00000001;
    hSrio->regs->LSU_ICCR = 0x00000001;
    hSrio->regs->LSU_ICRR[0] =0x00000001;
   myParamSetup.option = CSL_EDMA3_OPT_MAKE (CSL_EDMA3_ITCCH_DIS, /* enable the intermediate interruption */
                                              CSL_EDMA3_TCCH_DIS, \
                                              CSL_EDMA3_ITCINT_DIS, \
                                              CSL_EDMA3_TCINT_EN,/* enable the interruption of the final transfert */
                                              0, CSL_EDMA3_TCC_NORMAL,\
                                              CSL_EDMA3_FIFOWIDTH_NONE, \
                                              CSL_EDMA3_STATIC_DIS, \
                                              CSL_EDMA3_SYNC_A, \
                                              CSL_EDMA3_ADDRMODE_INCR, \
                                              CSL_EDMA3_ADDRMODE_INCR
                                             );
    myParamSetup.srcAddr = (Uint32)LSU_BUFFER;
    myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(24,6);
    myParamSetup.dstAddr = (Uint32)Adresse_Lsu_reg0;
    myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(24,32);
    myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
    myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(1, 1);
    myParamSetup.cCnt = 1;

I stored the 6 configurations that i wanted in LSU_BUFFER.

please help me to find why it doesn't work

0 Dieter Landl over 15 years ago in reply to Abdessamad

Prodigy 60 points

Abdo said:

HI Landl
Im using evm 6474

I did the configuration to route the interuption of SRIO to RIOINT1 , then i used the cic3 to route RIOINT1 to CIC _EVT4,
i did the configuration to the option field of parametre setup as shown in the code. but it doesn't work.

... snip

please help me to find why it doesn't work

Hello Abdo,

unfortunately I can't 'debug' your example caused by own project issues.

I'd like to encourage you to have a look at the DIO-library example for DIO_streamingReq

The Description states:

This is the DIO operation streaming request function. The function configures an array of LSU command configurations based on the number of bytes required by the data request. A single LSU command can handle up to 4096 bytes. This API configures the EDMA to automatically feed a LSU register set with a new command once the current one is completed. It assumes one of the available LSUs of the SRIO module is dedicated to DIO streaming. Also, the interrupt condition event for "No Error" completion code of this dedicated LSU shall be routed to a SRIO Interrupt Destination available at the EDMA. When the array of LSU command configurations is exhausted, the EDMA generates a CPU interrupt. This API only handles one stream at a time. The user specifies an EDMA streaming channel number (only 1 on CHIP_C6455, up to 4 on CHIP_C6457/6/8)

You'll find the DIO at

https://gforge.ti.com/gf/project/sriodirectiolib/scmsvn/?action=browse&path=%2Ftrunk%2FDIOLib_1_0_0.zip

select '(as text)' to download the zip file

I hope it helps

Regards

Dieter Landl

0 tarik taro over 15 years ago in reply to Eddie3909

Prodigy 80 points

hi SBANIC

i m really interested on how to use EDMA to overcome 4kbyte SRIO transfert.

do you have code for that ?thanks

tarik

0 Eddie3909 over 15 years ago in reply to tarik taro

Guru 10385 points

Hi Tarik

tarik taro said:

i m really interested on how to use EDMA to overcome 4kbyte SRIO transfert.

do you have code for that ?thanks

Download the DIO lib that Dieter Landl pointed you to and click on C:\Work\downloads\DIOLib_1_0_0\doc\DIOLibraryAPIReferenceGuide.html. Then select the "Modules" tab and then select "TST". It will explain all the test modules. Several of them demonstrate >4096 Byte transfers. An example would be the testDIO_edmaStreamLsu example.

Cheers

0 amar abderrahim over 15 years ago in reply to Eddie3909

Prodigy 105 points

hello everybody

i ve heard that we can stransfer a stream of data via SRIO and by using EDMA3 without using a doorbell interruption but just Events.

can you help me if you have an input in my issue.

thanks for your help

0 Eddie3909 over 15 years ago in reply to amar abderrahim

Guru 10385 points

Hi Amar

Each test has a testObj struct where you can specify if you want to use a doorbell or not. Look at the edmaStream example.

Cheers

0 amar abderrahim over 15 years ago in reply to Eddie3909

Prodigy 105 points

Hi Eddie,

thanks for your help, but do you have any idea about using events(of EDMA3) to transfer data on srio?

cheers

amar

0 Eddie3909 over 15 years ago in reply to amar abderrahim

Guru 10385 points

Hi Amar

Yes, but I'm sure you will find all you need to know about EDMA3 in the DIO library examples.

Cheers

0 Akash Bhatnagar over 14 years ago in reply to Eddie3909

Prodigy 20 points

HI all,

Can you please throw some light over following queries:-

1) Can this be possible that two SRIO PEs can send request type packets to each other especially NWRITE.

2) Just like EDMA channel 20 is used for synchronization with LSU interrupt, I want to synchronize either channel 19 or 21 with the receiving side.If peer-PE perform NWRITE_R and sends a data , I want to copy that data using EDMA to some memory location. After copying I want to interrupt the CPU that data is available for processing.

Can this is achievable? I am using TI6482 Processor.

Thanks

Processors

Processors forum

How to use EDMA for SRIO transfer on c6455/6474

Hello Mugiwara!