• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 101 subscribers
  • Views 1135 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Interfacing TMS320C6670 to an external ADC

Hardik Godara
Prodigy 140 points
Other Parts Discussed in Thread: TMS320C6670, ADS8881, ADS8329

Hi,

I have a TMS320C6670 DSP evaluation board (which doesn't have an internal ADC) and I need to interface an external ADC to it. My requirements are as follows:

I need at least 4 channels on the ADC where I will input 20-30 Khz four analog signals (having peak voltages around 1 V). The important criteria is to have simultaneous sampling and the sampling rate should be atleast 250 kSPS for each channel.

I can select the ADC but I am a bit confused for interfacing that ADC to DSP. Can anyone suggest an appropriate protocol (or a ADC evaluation board) for sending the ADC data to the mentioned DSP at higher rates so as to compensate the higher sampling rates?

  • 0
    TI__Mastermind 46460 points

    Hardik,

    The C6670 does not have a native CODEC interface.  This device is targeted at the wireless basestation market and that requires much higher bandwidth interfaces.  The AIF interface is specialized for this purpose.  I would recommend use of an FPGA to reformat the ADC sample data into a serial stream for transport.  You could then use any of the SERDES interfaces including simple SGMII or SRIO to transport the data into the C6670.  IP blocks for these interfaces are readily available from FPGA vendors.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 140 points

    Hi Tom,

    I very well acknowledge your answer and understand that FPGA based solution is one of the options. Can't I use a high speed ADC that uses an SPI interface to connect to c6670 DSP if I don't want to go for an FPGA? I saw a couple of ADCs like ads8329, ads8881 which have an SPI compatible serial interface and I intend to connect 4 such ADCs together on a single SPI port of DSP. Wouldn't that setup work and provide data at atleast 500-600 Khz per ADC given the fact that they are sharing the same SPI lines?

    And if not SPI, then what are the other options that I can opt for except for an FPGA?


    Hardik

  • 0 in reply to Hardik Godara
    TI__Mastermind 46460 points

    Hardik,

    Please clarify your expected data throughput.  You mentioned: "need at least 4 channels on the ADC where I will input 20-30 Khz four analog signals ... simultaneous sampling and the sampling rate should be at least 250 kSPS for each channel".  How many bits per sample?  I assumed the combined data throughput would be higher than 4 * 600Kbps per channel or 2.4Mbps.  If it is this low, then SPI is an excellent choice.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 140 points

    Well, I might choose 12, 16 or an 18 bit ADC (let's assume 16 bit now), hence the data throughput per channel will be at max 16*600kSPS (the sampling rate may go up to 600kSPS, so considering the max. value) or 9.6 Mbps and then the combined through put for four channels would be around 4*9.6 Mbps = 38.4 Mbps on a single SPI port of c6670. So please comment whether there would be any issues with SPI port of DSP for handling this configuration.


    Hardik

  • 0 in reply to Hardik Godara
    TI__Mastermind 46460 points

    Hardik,

    If you need sample captures at 600KSPS, at 16 bits per sample, then the SPI is close to the upper limit at a throughput of 38.4bps.  The SPI on the C6670 has a maximum SPI clock rate of CPU clock divided by 18.  Therefore, at max speed of 1.2GHz, this is 66.67MHz.  I also saw that the ADS8329 has a maximum SPI clock of 50MHz.  You will need to analyze the overhead needed.  I also recommend that you purchase a C6670 EVM and an ADS8329 EVM, wire them together and then evaluate the SPI configuration needed to support this streaming CODEC data flow.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 140 points

    Hi Tom,

    I have already bought a C6670 EVM. I will consider which ADC EVM to buy for sufficing my needs. Thanks for your help!


    Hardik

  • 0 in reply to Hardik Godara
    Prodigy 140 points

    Hi,

    I have a little query regarding the SPI protocol of  TMS320C6670 Evaluation Board. It seems to have two SPI buses, one for NOR and the other for FPGA. So while interfacing an external peripheral to it via SPI (let's take an example of an ADC), how do I ensure that the data that I get by pulling the CS low is indeed from the ADC and not from the FPGA which is connected on the same SPI bus?

    I am assuming that the FPGA has some startup boot sequence and configuration program for the DSP.

  • 0 in reply to Hardik Godara
    TI__Mastermind 46460 points

    Hardik,

    Please see the post at: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/212050.aspx.  A hardware mod will be needed to use SPI on the expansion header.

    Tom