Multi-segment SRIO Message Issues on C6472

Nick Borton

Hello,

I am current running into an odd problem when integrating a C6472 with a Xilinx FPGA. The FPGA is sending multi-segment SRIO messages, and the C6472 seems to be dropping the last segment if it is not 256 bytes long. I haven't noticed any restrictions in this regard in the user guide, but that doesn't mean I missed something. The last segment is sized correctly to a power of two between 8 and 256 inclusive.

Any ideas?

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi Norton,

Have you using TI evaluation module or customboard?

Are you using massage passing operation or Diract IO?

Please take a look at section 5.74 Port Error and Status CSR n (SPn_ERR_STAT) on SRIO user guide(SPRUE13J).

4505.TMS320C6472 TMS320TCI648x DSP srio.pdf

Thanks,

0 Nick Borton over 10 years ago in reply to Ganapathi Dhandapani95

Genius 3595 points

I am using a custom board with message passing.

I never get an interrupt in relation to the Port Error and Status CSR. I do get errors from here: Logical/Transport Layer Error Detect CSR. In particular I get Illegal Transaction Decode errors if the last segment of a multi-segment packet is not padded out to the full 256 bytes. I did not see that restriction anywhere in the user guide.

But then again, multi-segment messages are handled rather oddly in this part anyways.

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Multi-segment SRIO Message Issues on C6472