SRIO configuration

Hi,

I posted the following questions one week ago and I didn't receive any answer:

Hi,

I'm working with the internal loopback example found in the folder:

C:\Program Files\Texas Instruments\pdk_C6678_1_0_0_11\packages\ti\drv\exampleProjects\SRIO_LoopbackTestProject

1.- Could you tell me, please, which is the SRIO Bit Rate configured?

2.- Could you tell me, please, which is the lanes configuration?

Thanks in advance.

shmulik

The reference clock on the C6678 EVM is 312.5Mhz. 

Looking at C:\Program Files\Texas Instruments\pdk_C6678_1_0_0_11\packages\ti\drv\srio\device\device_srio_loopback.c we have:

CSL_BootCfgSetSRIOSERDESConfigPLL (0x235);
CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);
CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);

This actually yields a reserved MPY value.  This is a bug that has been previously reported and will be fixed in the next revision of the PDK release.  The correct values should be:

CSL_BootCfgSetSRIOSERDESConfigPLL (0x229);

CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);

CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);

Which yields a 3.125Gbps link rate.

For the C6670 EVM the reference clock is 250Mhz.  So the settings would be:

CSL_BootCfgSetSRIOSERDESConfigPLL (0x065);

CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x004404a5);

CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x001807a5);

Lane configuration is set by PATH_MODE, CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);  So this is being set to mode 0, which is 4 ports 1x mode.

Regards,

Travis

Hi the Rx and Tx setting part is not a bug,

the  0x01c40495 means loopback and 0x00440495 means not.

the tx parts too.

Also , I am too wandering the the ConfigPLL value.

hi'

When working with PATH_MODE = 0 and 5Gbps link rate, what will be the transfer rate:  5Gbps or 20Gbps?

Tuli

He,

Not sure if you have a question here?  The loopback inside the Serdes is not necessary since the code is already looped back in digital code.  If you want to disable loopback completely and run device to device, you would change the Serdes settings as I mentioned above, and you would make the following change:

    /* Configure SRIO ports to operate in loopback mode. */
 //   CSL_SRIO_SetLoopbackMode(hSrio, 0);
 //   CSL_SRIO_SetLoopbackMode(hSrio, 1);
 //   CSL_SRIO_SetLoopbackMode(hSrio, 2);
 //   CSL_SRIO_SetLoopbackMode(hSrio, 3);

    /* Configure SRIO to operate in normal mode. */
     CSL_SRIO_SetNormalMode(hSrio,0);
     CSL_SRIO_SetNormalMode(hSrio,1);
     CSL_SRIO_SetNormalMode(hSrio,2);
     CSL_SRIO_SetNormalMode(hSrio,3);

The PLL config value in the original example is not valid, I provided the necessary change for the EVMs at a specific datarate, you may have to change based on your required data rate.

Regards,

Travis

Tuli,

Path mode = 0, sets up the peripheral for 4 ports, each 1X wide.  Path mode = 4, sets the peripheral for 1 port 4X wide. See the below figure (C66x devices support Configuration 4)

The link rate is setup completely independent of the port width above and uses the SerDes registers.  As an example, if Path mode = 4, and the SerDes are setup for 5Gbps operation, you would have a single port giving you 20Gbps operation (max 16Gbps of theoretical bandwidth).

Hope that helps,

Travis

Hi Travis:

now I have two questions.

1. I am new to dsp coding so I don't understand the difference between loopback in DIGITAL CODE and loopback incide SERDES. Can you explain it or tell me where i can get explanation?

2. PLL value 229 = 0x 0000 0010 0010 1001

the bit 8-1 is 0001 0100. In the SRIO book it means 5x,  and 5 x 312.5mega is not 3.125giga.

That's why i say I am not so clear about the PLL value.

There is a TX to RX loopback capability in two places.  First, it can be done in digital logic before the Serdes.  This is controlled by RIO_PER_SET_CNTL1 bits 7:4.  Secondly, it can be done in the Serdes themselves using the Serdes_cfgtx and Serdes_cfgrx registers.

The 5x multiplier is not the only factor of the datarate, you must also consider the RATE field of the Serdes_cfgtx and Serdes_cfgrx registers.  The RATE basically determines how many samples per PLL clock.  This is documented in the SRIO user's guide.

Regards,

Travis

Hi Travis,

Regarding your answer to Tuli, I configured the Path mode to 4, the software stuck in the following line in the file device_srio_loopback.c:

    /* This code checks if the ports are operational or not. The functionality is not supported
     * on the simulator. */   
 for(i = 0; i < 4; i++)
        while (CSL_SRIO_IsPortOk (hSrio, i) != TRUE);

Please, could you tell me what do I need to configure in order to overcome this problem?

Thanks.

Shmulik

If you change to 1 port, you only need to check port_ok for 1 port not 4 ports.  This loop would not be needed, just check port0 port_ok.

Regards,

Travis

Hi Travis,

To check only one port I know, but my question was oriented what to do with the configuration of the three non used ports (SERDES Rx and Tx and so).

Thanks,

Shmulik.

Hi Travis,

In the orinal file device_srio_loopback.c the code that configures the loopback is:

    /* Configure SRIO ports to operate in loopback mode. */
    CSL_SRIO_SetLoopbackMode(hSrio, 0);

    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);

1- In this code there are two loops digital and serdes. Why?

2.- If I wanted to use only the SERDES loopback but NOT Digital Loopback I initialized Serdes_cfgtx , Serdes_cfgrx and RIO_PER_SET_CNTL1 as follow:

    CSL_SRIO_SetNormalMode(hSrio, 0);

    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);

    I don't know why but it didn't work. Please, could you tell me what must be the initialization?

3 - If I want to use only Digital loopback and not SERDES loopback the following configuration is ok?

    /* Configure SRIO ports to operate in loopback mode. */
    CSL_SRIO_SetLoopbackMode(hSrio, 0);

    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);

Thanks in advance.

Shmulik.

Shmulik,

In 1 port 4X mode, it still uses all 4 Serdes.  Think of it as one fat data pipe, where the data is spread across all four serdes lanes and sent across in parallel.  So, basically, the comment is that all SerDes have to be configured to run in this mode.  The only difference in the serdes settings for different size ports is that bit 20 of CFGTX (MSYNC), should be set as below:

Scenario 1 - A single aggregated port, four lanes wide (4X), we would set lane 0 MSYNC = 1, lanes 1, 2, 3 MSYNC = 0

Scenario 2 - Two aggregated ports each two lanes (two 2X ports), we would set lane 0  and lane 2 MSYNC = 1, lanes 1 and 3 MSYNC = 0

Scenario 3 - four single ports (four 1X ports), we would set lanes 0,1,2,and 3 = 1

Shmulik said:

In the orinal file device_srio_loopback.c the code that configures the loopback is:

    /* Configure SRIO ports to operate in loopback mode. */
    CSL_SRIO_SetLoopbackMode(hSrio, 0);

    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);

1- In this code there are two loops digital and serdes. Why?

Not sure why this was done.  It will be using the digital loopback though.

Shmulik said:

2.- If I wanted to use only the SERDES loopback but NOT Digital Loopback I initialized Serdes_cfgtx , Serdes_cfgrx and RIO_PER_SET_CNTL1 as follow:

    CSL_SRIO_SetNormalMode(hSrio, 0);

    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);

    I don't know why but it didn't work. Please, could you tell me what must be the initialization?

Are you initializing all the Serdes on just serdes 0?  As I mentioned above, you need all the Serdes initialized.

Shmulik said:

3 - If I want to use only Digital loopback and not SERDES loopback the following configuration is ok?

    /* Configure SRIO ports to operate in loopback mode. */
    CSL_SRIO_SetLoopbackMode(hSrio, 0);

    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);

Yes.  But like I said if you have both serdes and digital loopback enabled, it will use the digital because it is sitting before the serdes.

Regards,

Travis

Hi,

I configured the SRIO ports in X1 configuration (4 ports, each 1X wide) LOOPED ONLY IN SERDES as described bellow:

    /* Configure SRIO ports to operate in loopback mode. */
    CSL_SRIO_SetNormalMode(hSrio, 0);
    CSL_SRIO_SetNormalMode(hSrio, 1);
    CSL_SRIO_SetNormalMode(hSrio, 2);
    CSL_SRIO_SetNormalMode(hSrio, 3);

    /* Assuming the link rate is 5000; program the PLL accordingly. */
    CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x01C40495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);
    CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00780795);
    CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00780795);
    CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00780795);

// MSYNC =1 for all the ports.

 /* Configure the path mode for the ports. */
    for(i = 0; i < 4; i++)
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);

but the routine stuck in in the loop and never goes out:

       while (1)
        {
            /* Get the completion code. */
            if (Srio_getSockOpt(srioSocket, Srio_Opt_DIO_SOCK_COMP_CODE, &compCode, sizeof(uint8_t)) < 0)
            {
                System_printf ("Error: Unable to get the completion code\n");
                return -1;
            }

            /* Was the transfer complete? */
            if (compCode != 0xFF)
                break;
        }

Please, could you tell me what should be the problem, because I think the configuration is ok.

Thanks.

Shmulik.

Shmulik,

This is happening on the very first LSU transaction?  To me, it seems the packet isn't being sent out if you are not getting a completion code.  The port_ok must be getting set to even make it this far in the program since you are sending packets.  This would mean the configuration is good.  Not sure why you are seeing it with the initial run after a board POR.  If you are doing a reset and this problem is after that, make sure again that you are doing the SRIO reset isolation fix before resetting.  That could explain it.  Another thing to try is send a NWRITE_R or NREAD type packet.  Since these have responses, you should at least see a CC=0b001 (timeout), which would kick you out of that loop.  If you are stuck in this while loop when using one of these type packets, then it would appear the writes to the LSU are not even occurring.

Regards,

Travis

Hi Travis,

Please could you answer me the following question?

If I configure the SRIO Loopback example according to:

  /* Configure SRIO ports to operate in loopback mode. */
    CSL_SRIO_SetNormalMode(hSrio, 0);
    CSL_SRIO_SetNormalMode(hSrio, 1);
    CSL_SRIO_SetNormalMode(hSrio, 2);
    CSL_SRIO_SetNormalMode(hSrio, 3);

    /* Assuming the link rate is 5000; program the PLL accordingly. */
    CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x01C40495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);
    CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00780795);
    CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00780795);
    CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00780795);

// MSYNC =1 for all the ports.

 /* Configure the path mode for the ports. */
    for(i = 0; i < 4; i++)
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);

Could you tell me, please, which will be the theorist bit rate in the example?

Thanks in advance.

Shmulik.

Shmulik,

In this mode, you are in Serdes loopback, I believe each port is 5Gbaud, yielding theoretical max of 4Gbps datarate not including packet overhead.  Depending on the packet type you use and the size of the transfers, your throughput will vary.  We will be releasing a benchmark app note and the actual code we used soon.  But from the data I've seen, you can expect to hit around 92% of the max bandwidth on a single 1X link at 5GBaud if using 512B transfers or greater.

Hope that helps,

Travis