c6670 SPI NOR boot

Hi Ronengi, 

Have you tried to place the code in MSMC and see if the boot completes?

Have you verified the SPI writes to the NOR flash by reading back the data.

Can you probe the SPI data lines and check if you see data on the lines when the clock is provided?

Are you using the default SPI parameter table to boot the device?

Thanks.

Hi Rajasekaran

1. Didn't try MSMC

2. Yes, verified.

3. There is data on the lines constantly

4. What are the default parameters? How do I generate this parameter table and combine with my code?.

Best,

Ronen

Tried MSMC, still not working.

BOOTCOMPLETE 0. DEVSTAT: D40D

Best,

Ronen

Hi Rahul,

Thank you for the info and example. I did that but it looks like the RBL is not completing the boot process.

What is the exact process for making a boot image with no IBL involved? My code is compiled as little endian and I used the ccs2bin -swap command to change it to big endian for the RBL as instructed. Is it the correct way to do it?

Any other suggestions?

Best,

Ronen 

DId you try the example on the EVM?  Did you use the ROM SPI boot settings from the wiki page

http://processors.wiki.ti.com/index.php/TMDXEVM6670L_EVM_Hardware_Setup#Boot_Mode_Dip_Switch_Settings

Please mention the value of the program counter and the DEVSTAT register. I want to confirm that you have set the boot pins to SPI boot and the RBL is executing code for SPI. 

Regards,

Rahul

Hi,

The boot is working after I made changes to the parameter table file (*.map).

Changed mode from 0 to 1.

I am not sure about the parameters in the 8.rmd file.

This is what I'm using for my program:

ARC1_CHA.out
-a
-boot
-e _c_int00

ROMS
{
   ROM1:  org = 0x0C000000, length = 0x200000, memwidth = 32, romwidth = 32
          files = { spiboot.btbl }
}  

What do I need to change in order to work with L2SRAM?

Thanks,

Ronen

Hi Rahul,

Thank you for your help.

Best,

Ronen

Hi Rahul,

Sorry for interrupting you.

I have a question about SPI_Bootloader.zip which you attached to this post.
There nysh.spi.map inside this zip file.

My question is about the nysh.spi.map.
In nysh.spi.map, there are following parameter for PLL.
===============================
* sw_pll_prediv
* sw_pll_mult
* sw_pll_postdiv
* sw_pll_flags
===============================
Which PLL register does these parameter affect to?

And I want to speed up the SPI bus frequency.
At default it looks like the RBL will setup the SPI bus frequency to 20MHz..
For example, if I want to setup to 50.5MHz, is the following configuration correct?
======================
* bus_freq_mhz = 50
* bus_freq_khz = 500
======================

best regards,
g.f.

g.f. said:

In nysh.spi.map, there are following parameter for PLL.
===============================
* sw_pll_prediv
* sw_pll_mult
* sw_pll_postdiv
* sw_pll_flags
===============================
Which PLL register does these parameter affect to?

The above software flags in the nysh.map file are used to configure the main PLL on C66x device. These registers will primarily configure PLL_CTL , PREDIV, PLLM registers using the PLL initialization sequence specified in the PLL USer Guide. 

To see the complete  list of PLL registers these parameters impact please take a look at the hwPllsetPll function in pll.c file in the Gauss boot ROM source(hw/pll directory). The Gauss boot ROM source is provided on the wiki page below:

http://processors.wiki.ti.com/index.php/Keystone_Device_Architecture#Keystone_ROM_Boot_Examples_and_Reference_code

g.f. said:

And I want to speed up the SPI bus frequency.
At default it looks like the RBL will setup the SPI bus frequency to 20MHz..
For example, if I want to setup to 50.5MHz, is the following configuration correct?
======================
* bus_freq_mhz = 50
* bus_freq_khz = 500
======================

The bus_freq_mhz and bus_freq_khz configure the busFreqMhz and busFreqKhz parameter  of the boot parameter table for SPI boot. If you look into the tiboot.h file for the ROM, you can see the usage specified as shown below

UINT16 busFreqMhz; /* The speed of the SPI bus, the megahertz portion */
UINT16 busFreqKhz; /* The KHz portion of the bus frequency. A frequency of 1.5 MHz would have the value 5 here */

So you are right to configure it to 50.5 Mhz  you should set these using the settings that you have mentioned in your post.

Regards,

Rahul

Hi Rahul,

Thank you so much for the reply.

I checked the boot ROM source code. From the source code, I understood that
swi_pll_prediv will affect to MAINPLLCTL0.PLLDIV and
swi_pll_mult will affect to MAINPLLCTL0.PLLM.
I guess there is no register for sw_pll_postdiv in C6670.

By the way, I'm able to get SPI bus clock(10.5MHz) which I expected by configuring the
parameter as follow:
(I checked the clock by using oscilloscope)
*sw_pll_prediv = 1
*sw_pll_mult = 32
*sw_pll_flags = 1

*bus_freq_mhz = 10
*bus_freq_khz = 500

But when I checked the Main PLL register from CCSv5 memory browser,
the PLL_Mult and PLL_DIV bit value was set to zero.
Do you know why it was set to zero?

best regards,
g.f.

The main PLL stays in bypass mode for no-boot, SPI, and I2C boot. For other boot modes, a PLL initialization sequence executes inside the boot ROM to configure the main PLL in PLL mode.

Regards,

Rahul

Hi Rahul,

Thank you for the reply.

I understood that PLL is in bypass mode if SPI/I2C boot are used.
But I thought if setting the pll parameter in Boot parameter table,
RBL will first read this table from SPI NOR flash to internal memory(L2) and
then set the PLL controller to the expected value.
So, is this understanding wrong? Then why there are pll parameter in Boot parameter table?

Do you mean that PLL is in bypass mode and RBL won't change if SPI boot is used,
but RBL will change SPI bus frequency to expected speed?

In C6670EVM input clock is 122.88MHz, so that CorePac0 is running at 122.88MHz(bypassed)
and SPI module clock are 20.48MHz. So, is 20.48MHz the maximum SPI bus frequency in EVM SPI boot mode?

best regards,
g.f.

Hi Rahul,

I'm sorry for asking again but
can you please reply to my last question?

best regards,
g.f.