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question about c6678's FPGA

Other Parts Discussed in Thread: UCD9222

hi, all:

in the ti's "TMDSEVM6678Lx_EVM_REV_3_0_Known_Issues": 2.6  The FPGA code update issue on the EVMs,

it says: "The FPGA cannot be reprogrammed while the UCD9222 contains a configuration and it is operating.  One solution requires erasing the configuration from the UCD9222 before programming the FPGA.  The alternate and preferred solution is reprogramming the FPGA from the DSP with CCS connected."

So I have 2 questions about this:

1. why cant't the FPGA be programmed while the UCD9222 has configuration? When the FPGA is programmed, will the 6678's core voltage be changed? or some other reason?

2. The CCS the FPGA can be reprogrammed, can anyone tell me in what way or path the FPGA get programmed, how does it work?

Thanks!

 

  • Hi Shore,

    We discovered the problem programming the FPGA while the UCD9222 was configured during the testing of the board but we didn't determine the cause. Since the FPGA is programmed during initial manufacturing it wasn't blocking our progress. 

    Can you tell my why you need to reprogram the FPGA? Note that we don't support custom builds of FPGA code on the EVM. The only FPGA code that can be programmed into the device is the bit file available on the Advantech website.

    Regards, Bill

  • Hi, Bill:

      Thanks for reply.

      I need to program the FPGA because I design a system based on 6678. According to the article, when I

    modify my fpga code, first I have to erase the ucd9222 configuration, that is inconvenient. On the other hand,

    after erasing the ucd9222's configuration, does the ucd9222 continue outputing the CVDD voltage to 6678?

    if it does, what value it outputs? 1.1V or something else?

    Then the 2nd question, if I program the FPGA from the CCS, what is needed except the applet you provide?

    How does the CCS download the code to FPGA, what hardware component is needed on my board except JTAG?You see, I can't figure out how the CCS downloads the code to FPGA.

  • Hi Shore,

    The FPGA programming code is specific to the EVM. It is not designed as general purpose code for a customer design. Also note that the problem with programming the FPGA when a UCD9222 configuration is present is also specific to the EVM. I can't tell you if you will see the same problem on your board since the issue was never root-caused. This only applied to programming the FPGA using the external Xilinx programming pod. If the FPGA was programmed using the SOC we didn't see this problem. Since the Xilinx pod was only used during the production cycle of the board, we programmed it before the UCD9222 configuration was present. 

    Regards, Bill

  • hi, Bill:

      Thanks for reply!

      In your reply, you mentioned "If the FPGA was programmed using the SOC we didn't see this problem."

      So if I have the EVM at hand, Could you show me how to program the FPGA in the CCS step by step?

    or tell me which document show this procedure.

     

  • Hi Shore,

    I think you misunderstood my comment. Initial programming of the FPGA is done using the JTAG interface and a Xilinx programming tool. The FPGA on the EVM is configured from the internal FLASH which is non-volitile and doesn't need to be reprogrammed after the devices is powered down. The ability to program the FPGA from the SOC is part of the FPGA programming and is not present until after the FPGA is configured for the first time using JTAG. The software used to reprogram the FLASH in the FPGA is an internal tool and is not provided to customers. If you have included a Xilinx Spartan3AN FPGA in your design, you can find information on how to include the capability for reprogramming the internal configuration FLASH in Xilinx document UG333.  

    Regards, Bill